Tri-Mode Local Accumulator

• Tri-Mode Local Accumulator is a configurable mechanism that supports three distinct operating modes to reconcile precision, throughput, and hardware limitations.
• It enables trans-precision accumulation in FP32 datapaths, adaptive spiking in neuromorphic systems, and efficient charge-sharing in SRAM-based computing-in-memory.
• The design strategically defers rounding and optimizes error propagation across stages, balancing numerical accuracy with energy and area efficiency.

A Tri-Mode Local Accumulator is a local accumulation mechanism with three selectable operating modes or stages, used to reconcile throughput, numerical behavior, and hardware cost under constrained datapaths. In the available literature, the term has no single universal definition. In reconfigurable floating-point hardware, it denotes a single local FP32 accumulator embedded in an FPU that reduces either 2 FP16, 4 FP8, or 8 FP4 products per cycle into one FP32 result; in neuromorphic sparse inference, it denotes a gradual transition among graded, intermittent, and tonic spiking regimes controlled by spike height; in computing-in-memory, it denotes three accumulation modes—bit-slicing, PWM, and bit-slicing with charge-sharing-based weighted accumulation; and in accumulator-aware post-training quantization, it is a natural specialization of generic multi-stage accumulation into three local stages (Wang et al., 8 May 2026, Parpart et al., 2022, Yang et al., 29 May 2026, Colbert et al., 2024).

1. Terminology and conceptual scope

The term is used most concretely in TransDot, where tri-mode local accumulation refers to a single, local FP32 accumulator embedded in the FPU that can be reconfigured to consume and reduce 2 FP16 products, 4 FP8 products, or 8 FP4 products per cycle into one FP32 result (Wang et al., 8 May 2026). The core idea there is trans-precision accumulation: low-precision inputs are accumulated in an FP32 datapath and rounded once at the end.

In other domains, the same phrase is better understood as a unifying description rather than a standardized name. In spiking dictionary learning, the paper introduces accumulator neurons and explicitly describes three operating regimes—graded/analog, intermittent/bursty spiking, and tonic/sustained single-spike mode—governed by the spike height $s$ (Parpart et al., 2022). In SRAM computing-in-memory, the macro exposes three modes of accumulation and reconfiguration: bit-slicing, PWM, and BSCHA (Yang et al., 29 May 2026). In accumulator-aware PTQ, the paper explicitly states that it does not use the term “tri-mode,” but that AXE’s multi-stage accumulation maps cleanly to a design with three local accumulation stages (Colbert et al., 2024).

A plausible implication is that “Tri-Mode Local Accumulator” is best treated as a family resemblance across architectures: three local accumulation behaviors are exposed to match a fixed external interface while changing the internal reduction schedule, precision, or temporal sparsity.

Context	Local accumulator	Three modes or stages
Reconfigurable FPU	Single FP32 local accumulator	FP16×2, FP8×4, FP4×8 DPA
Neuromorphic S-LCA	Residual accumulator state per neuron	Graded, intermittent, tonic
SRAM CIM macro	Local capacitor-based accumulator	BS, PWM, BSCHA
Accumulator-aware PTQ	Local staged accumulators	Intra-tile, block, output stage

2. Floating-point tri-mode local accumulation in TransDot

In TransDot, tri-mode local accumulation is implemented as a fused dot-product engine embedded in a reconfigurable FP32 datapath (Wang et al., 8 May 2026). The general fused dot-product accumulation into FP32 is written as

$$s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{N} a_i \cdot b_i\right),$$

with tri-mode instances $N=2,4,8$. The three explicit cases are

$$s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{2} a_i \cdot b_i\right), \quad s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{4} a_i \cdot b_i\right), \quad s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{8} a_i \cdot b_i\right),$$

corresponding respectively to FP16$\rightarrow$FP32, FP8$\rightarrow$FP32, and FP4$\rightarrow$FP32. For contrast, the non-fused variants round each product before summation.

The architecture avoids replicating independent FMA lanes. Instead, it reuses internal subword parallelism so that scalar, SIMD, and DPA all inhabit the same wide FP32 datapath. Large alignment and normalization shifters are converted to reconfigurable, partitionable structures supporting full-width, two half-width, and four quarter-width operation. The FP32 mantissas are partitioned into four 6-bit segments in a multi-mode array multiplier that generates $8\times 12$-bit and $2\times 24$-bit partial products once and then selectively gates or combines them across scalar FP32, low-precision SIMD, and tri-mode DPA. FP4 support is provided by a compact FP4 DP2 stage that computes the products of two FP4 pairs in sign–magnitude form and forwards four 9-bit partial products into the shared reduction network.

Mode selection configures partition widths, active term count, and operand routing while preserving a fixed input/output width, so the unit emits one FP32 result per cycle in all modes. In FP16-DPA, two FP16 operand pairs are packed; FP8-DPA packs four E4M3 pairs; FP4-DPA packs eight E2M1 pairs. The exponent datapath sets an anchor exponent and computes per-term alignment shifts so that each product is aligned before reduction. This design is explicitly bandwidth-balanced for AMD Versal AI engines, because one FP32 result per cycle is maintained without widening the output interface.

Quantitatively, the design delivers $2\times$ FP16, $$s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{N} a_i \cdot b_i\right),$$0 FP8, and $$s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{N} a_i \cdot b_i\right),$$1 FP4 throughput via DPA with FP32 accumulation. It reports $$s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{N} a_i \cdot b_i\right),$$2 area efficiency in FP16 DPA and $$s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{N} a_i \cdot b_i\right),$$3 area efficiency in FP8 DPA, at the cost of 37.3% larger area on average and an additional pipeline stage in dot-product mode compared to the FPnew baseline. Post-P&R at 12 nm, 1 GHz, 0.8 V, TT corner, the reported operating points are 4 GFLOP/s and 1.80 pJ/FLOP for FP16 DPA$$s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{N} a_i \cdot b_i\right),$$4FP32, 8 GFLOP/s and 0.84 pJ/FLOP for FP8 DPA$$s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{N} a_i \cdot b_i\right),$$5FP32, and 16 GFLOP/s and 0.41 pJ/FLOP for FP4 DPA$$s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{N} a_i \cdot b_i\right),$$6FP32 (Wang et al., 8 May 2026).

3. Numerical semantics: fused reduction, precision retention, and accumulator sizing

The defining numerical property of the TransDot realization is that the entire dot-product reduction is performed in the high-precision datapath with a single, IEEE-754-consistent normalization and rounding (Wang et al., 8 May 2026). The stated rationale is twofold: intermediate sums retain more significand bits and dynamic range than in low precision, and rounding is deferred to the end of the reduction, avoiding compounding rounding error across partial sums. The design propagates guard/round/sticky information through alignment and reduction so that round-to-nearest, ties-to-even can be applied accurately in the final stage.

The internal reduction path is provisioned at FP32 widths. Using $$s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{N} a_i \cdot b_i\right),$$7 mantissa_bits $$s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{N} a_i \cdot b_i\right),$$8, the alignment shifter is $$s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{N} a_i \cdot b_i\right),$$9 bits, which is 100 bits for FP32 with $N=2,4,8$0. The aligned addition range is $N=2,4,8$1 bits, which is 76 bits for FP32. The post-normalization shifter is $N=2,4,8$2 bits, which is 77 bits for FP32. Carry-save reduction is used inside the multiplier tree, followed by a final carry-propagate addition. Format-specific special-case handling for NaN, Inf, subnormals, and sign rules is implemented as lightweight peripheral logic, and in DPA mode these checks ensure that invalid products or infinities propagate correctly to the FP32 output.

The numerical motivation has analogues in the other realizations. In accumulator neurons, the residual accumulator carries discretization error forward rather than discarding it, which bounds instantaneous mismatch. In BSCHA, repeated local ADC conversions are replaced by analog recombination before a single final conversion. In AXE, overflow risk is managed by explicit per-stage bounds rather than by assuming an oversized monolithic accumulator. This suggests that tri-mode local accumulation, across domains, is defined as much by when and where reduction is finalized as by the existence of three modes.

4. Neuromorphic realization: accumulator neurons and three dynamical regimes

In “Dictionary Learning with Accumulator Neurons,” an accumulator neuron combines a conventional leaky-integrate-and-fire spike generator with an additional residual accumulator state that is used to minimize the difference between the integrated input and the spiking output (Parpart et al., 2022). Let $N=2,4,8$3 be the desired analog output, $N=2,4,8$4 the spike height, and $N=2,4,8$5 the residual accumulator state. A discrete-time realization consistent with the paper’s description is

$N=2,4,8$6

An alternative floor-based realization is also given. The local objective is to minimize the instantaneous discretization error

$N=2,4,8$7

Within LCA/S-LCA, sparse coding seeks

$N=2,4,8$8

with rectifying soft-threshold activation

$N=2,4,8$9

The spiking version replaces rate-coded $$s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{2} a_i \cdot b_i\right), \quad s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{4} a_i \cdot b_i\right), \quad s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{8} a_i \cdot b_i\right),$$0 with accumulator-based discretized spiking output and typically applies a low-pass filter or moving average,

$$s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{2} a_i \cdot b_i\right), \quad s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{4} a_i \cdot b_i\right), \quad s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{8} a_i \cdot b_i\right),$$1

for reconstruction and learning stability.

The paper identifies three regimes implied by spike-height control. In graded/analog mode, $$s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{2} a_i \cdot b_i\right), \quad s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{4} a_i \cdot b_i\right), \quad s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{8} a_i \cdot b_i\right),$$2, and the neuron behaves like the original non-spiking unit. In intermittent/bursty spiking mode, moderate $$s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{2} a_i \cdot b_i\right), \quad s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{4} a_i \cdot b_i\right), \quad s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{8} a_i \cdot b_i\right),$$3 yields bounded-error spike bursts that preserve average output over time. In tonic/sustained single-spike mode, large $$s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{2} a_i \cdot b_i\right), \quad s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{4} a_i \cdot b_i\right), \quad s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{8} a_i \cdot b_i\right),$$4 produces at most one spike per timestep and resembles conventional LIF behavior. Reported examples include CIFAR with $$s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{2} a_i \cdot b_i\right), \quad s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{4} a_i \cdot b_i\right), \quad s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{8} a_i \cdot b_i\right),$$5 and 100 ms low-pass smoothing, and Poker-DVS with $$s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{2} a_i \cdot b_i\right), \quad s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{4} a_i \cdot b_i\right), \quad s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{8} a_i \cdot b_i\right),$$6 and 40 ms moving average. The reported maximum spikes per timestep drop from approximately 70 at $$s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{2} a_i \cdot b_i\right), \quad s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{4} a_i \cdot b_i\right), \quad s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{8} a_i \cdot b_i\right),$$7 to approximately 1 at $$s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{2} a_i \cdot b_i\right), \quad s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{4} a_i \cdot b_i\right), \quad s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{8} a_i \cdot b_i\right),$$8.

The empirical results support the three-regime interpretation. For CIFAR-10 with 16×16 center-cropped images and a dictionary of 3840 features, LCA sparsity is 1.82% and S-LCA at $$s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{2} a_i \cdot b_i\right), \quad s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{4} a_i \cdot b_i\right), \quad s = \mathrm{round}_{32}\!\left(\sum_{i=1}^{8} a_i \cdot b_i\right),$$9 is 2.17%. Reconstruction RMSE is 0.0195 for LCA, 0.0779 for S-LCA without smoothing, and 0.0167 for S-LCA with 100 ms low-pass smoothing. For Poker-DVS with 35×35 DVS frames, 1 ms frames, and 5-frame windows, validation RMSE at $\rightarrow$0 and dictionary size 1/2 under-complete is reported as 0.3788, 0.4810, 0.6405, and 0.9958 without averaging for $\rightarrow$1, while the corresponding 40 ms averaged RMSE values are 0.4012, 0.3629, 0.3592, and 0.3558. The classification result at 1/2 under-complete and $\rightarrow$2 is 92.2% $\rightarrow$3 0.8 across runs for LCA, and the paper reports essentially no degradation in performance as the model migrates from graded to spiking when smoothing is applied.

5. Charge-sharing local accumulation in SRAM computing-in-memory

In “A Reconfigurable Computing In-Memory Macro with Charge-sharing-based Weighted Accumulator,” the local accumulator is a capacitor-based near-memory network in a 256×128 SRAM macro (Yang et al., 29 May 2026). The macro contains 256 rows × 127 MAC columns of dual-8T SRAM bitcells plus one 256×1 reference column for the IMADC. Each differential MAC column includes two near-memory MOM capacitors, $\rightarrow$4 and $\rightarrow$5, each approximately 50 fF, forming a local accumulator network. The three accumulation modes are bit-slicing, PWM, and BSCHA.

In bit-slicing mode, an $\rightarrow$6-bit input is decomposed into bit-planes, each partial sum is digitized separately, and digital recombination forms

$\rightarrow$7

The total latency is

$\rightarrow$8

cycles, and the conversion energy is

$\rightarrow$9

In PWM mode, the input is encoded as pulse width $\rightarrow$0, and the charge contributed by a cell is

$\rightarrow$1

The general charge-sharing voltage relation is written as

$\rightarrow$2

which in the current-domain SRAM case simplifies to the linear discharge approximation. PWM latency is

$\rightarrow$3

In BSCHA mode, bit-sliced input presentation is retained, but binary weighting is accumulated locally in analog before ADC by charge sharing between equal capacitors. The key recurrence is

$\rightarrow$4

and after $\rightarrow$5 bits,

$\rightarrow$6

A single IMADC conversion is then performed. The reported latency and energy models are

$\rightarrow$7

The reported quantitative advantages are specific. Under $\rightarrow$8, BS requires $\rightarrow$9 cycles, PWM requires $\rightarrow$0, and BSCHA requires $\rightarrow$1. For $\rightarrow$2, BSCHA is 135 cycles versus PWM 256 and BS 896, corresponding to 1.9× lower latency than PWM and 6.6× lower latency than BS. The BSCHA mode also reports approximately 23× better VMAC linearity than PWM under multi-bit input. At the macro level, throughput is reported as 14 GOPS at 7/4/7, 98 GOPS at 4/4/4, and up to 6502 GOPS at 1/2/1. The IMADC occupies approximately 3% of MAC-array area, a 9× reduction relative to a 27% overhead prior IMADC, and the read-wordline under-driven cascode improves unit-current linearity by 7× while increasing usable read-bitline voltage swing by 3.5×.

6. Generalization to staged accumulation in accumulator-aware PTQ

In “Accumulator-Aware Post-Training Quantization,” the paper explicitly states that it does not use the term “tri-mode,” but it introduces a generic multi-stage accumulation framework that maps naturally onto a three-stage local design (Colbert et al., 2024). The fixed-point dot-product accumulator is

$\rightarrow$3

with worst-case magnitude bounded by

$\rightarrow$4

AXE replaces crude datatype-only bounds with accumulator-centric constraints based on positive and negative weight budgets. For unsigned activations, the safe bounds reduce to

$\rightarrow$5

where $\rightarrow$6 is the sum of positive quantized weights and $\rightarrow$7 the sum of negative quantized weights. Greedy quantization then constrains each selected $\rightarrow$8 to

$\rightarrow$9

with rounding guard

$8\times 12$0

The multi-stage result is central for tri-stage interpretations. If a dot product of depth $8\times 12$1 is partitioned into tiles of size $8\times 12$2, each inner sum fitting a $8\times 12$3-bit accumulator, then the minimum outer accumulator width is

$8\times 12$4

The paper then gives an explicit mapping to three stages: Mode 1 intra-MAC tile accumulation, Mode 2 block/group reduction of tile partial sums, and Mode 3 layer/output-level accumulation, with sizing rules such as

$8\times 12$5

Empirically, AXE improves the trade-off between accumulator bit width and model accuracy over baseline PTQ methods. Reported examples include ResNet18 on ImageNet with 69.3% Top-1 at $8\times 12$6 using W5A6 under AXE+GPFQ versus 67.3% for EP-init, ViT-B-32 with 75.8% at $8\times 12$7 using W6A8 versus 72.7% for EP-init, and OPT-125M with perplexity 29.3 at $8\times 12$8 using W5A7, compared with FP32 perplexity 27.7. For Pythia models up to 6.9B, the paper reports that multi-stage accumulation with inner $8\times 12$9 and tiles $2\times 24$0 remains close to unconstrained PTQ baselines, whereas a monolithic 16-bit accumulator causes severe degradation and instability as width grows.

7. Trade-offs, limitations, and recurring misconceptions

A recurring misconception is that a tri-mode local accumulator is a single fixed circuit pattern. The literature instead shows several non-equivalent realizations. In TransDot, the three modes are term counts and precisions within one FP32 fused reduction path. In accumulator neurons, the three modes are dynamical regimes set by spike height $2\times 24$1. In the SRAM CIM macro, the three modes are distinct accumulation-and-conversion strategies. In AXE, “tri-mode” is not the paper’s own term, but a natural specialization of its multi-stage accumulation framework (Wang et al., 8 May 2026, Parpart et al., 2022, Yang et al., 29 May 2026, Colbert et al., 2024).

A second misconception is that tri-mode behavior is purely about throughput. In the floating-point case, numerical stability is central because rounding is deferred to the end of a fused FP32 reduction. In the neuromorphic case, residual error carry-forward preserves the time-average analog target and allows smoothing to recover reconstruction and classification performance. In the CIM case, BSCHA reduces ADC count and keeps bitline swing small, improving linearity. In AXE, the main issue is formal overflow avoidance under constrained accumulators rather than raw speed.

The limitations are likewise domain-specific. TransDot incurs 37.3% average area overhead versus FPnew and adds one pipeline stage in DPA mode. Its supported tri-mode counts are limited to FP16×2, FP8×4, and FP4×8; more than 8-term DPA would require further changes to the reduction tree and control. Accumulator-neuron systems trade spike rate against latency because larger $2\times 24$2 lowers event rate but requires smoothing windows of 40–100 ms for stable reconstruction and learning. The CIM macro’s multi-bit weights require parallel ternary-cell composition, increasing cell count for higher precision, and PWM remains slow and less linear. AXE’s worst-case budgeting is conservative, requires activation quantization, and demands careful inclusion of bias and residual paths in the final-stage bound.

Taken together, these realizations support a narrow but useful characterization: a Tri-Mode Local Accumulator is a locality-preserving accumulation mechanism that exposes three internal reduction modes or stages in order to balance interface constraints against precision, latency, energy, or overflow risk. The common strategy is not merely to add partial products, but to structure where accumulation occurs, how error is carried, and when final conversion or rounding is permitted.