DTSA: Deterministic Threshold-Based Scaled Adder

• DTSA is a deterministic threshold-based scaled adder that replaces approximate MUX methods in hybrid temporal computing for improved summation accuracy.
• It integrates into E-HTC MAC architectures, supporting both unipolar and bipolar encodings to enhance performance in FIR and DCT applications.
• DTSA employs threshold logic to deterministically assess temporal bitstreams, achieving up to 94% accuracy improvements while reducing power and area.

The Deterministic Threshold-based Scaled Adder (DTSA) is a deterministic summation mechanism introduced within the Enhanced Hybrid Temporal Computing (E-HTC) framework for ultra-low-power hardware accelerators. In that framework, DTSA is presented as a replacement for the MUX-based scaled addition used in prior Hybrid Temporal Computing (HTC) architectures, which the source paper identifies as a cause of accuracy loss. DTSA is defined as a scaled-adder architecture that employs threshold-based logic for scaled addition, is integrated into a multiplier–accumulator (MAC) supporting both unipolar and bipolar encodings, and is evaluated in MAC-, FIR-, and DCT/iDCT-based accelerators (Sachdeva et al., 26 Sep 2025).

1. Origin within Enhanced Hybrid Temporal Computing

DTSA arises from a specific limitation of earlier HTC designs. HTC is described as leveraging pulse-rate and temporal data encoding to reduce switching activity and energy consumption, but its original form performs scaled addition with a multiplexer (MUX). The cited paper states that HTC “suffers accuracy loss due to its use of a multiplexer (MUX) for scaled addition,” and frames E-HTC as a response to that deficiency (Sachdeva et al., 26 Sep 2025).

The central issue is not multiplication but accumulation. A MUX-based adder is hardware-efficient, yet it realizes scaled addition only statistically or approximately, because each cycle depends on which input stream is selected rather than on a deterministic aggregation of all active inputs. In MAC-heavy workloads such as FIR filtering and DCT/iDCT, these local summation errors accumulate and degrade application-level metrics such as RMSE and PSNR. DTSA is therefore motivated by the need for a summation operator that preserves the low-power temporal/bitstream style of HTC while replacing selection-induced stochastic error with deterministic behavior.

Within E-HTC, DTSA is one of two deterministic adders. The other is the Exact Multiple-input Binary Accumulator (EMBA), which is explicitly described as performing precise binary accumulation. DTSA occupies a different point in the design space: it is deterministic and accuracy-oriented, but the supplied text does not describe it as “exact” in the same sense as EMBA. This distinction is significant for interpreting both the claims and the reported results.

2. Definition and Functional Principle

The formal definition available in the supplied text is narrow but clear: DTSA is a “Deterministic Threshold-based Scaled Adder (DTSA), which employs threshold-based logic for scaled addition” (Sachdeva et al., 26 Sep 2025). That formulation establishes three properties.

First, DTSA operates on multiple input bitstreams in a temporal or pulse-rate computing context. Second, its output is generated by threshold-based logic, not by random or arbitrary input selection. Third, its purpose is scaled addition, meaning that the output represents a scaled sum rather than an unrestricted exact arithmetic accumulation.

From the text, the operational description that can be stated faithfully is limited to the following sequence: multiple temporally encoded or pulse-rate encoded bitstreams are presented to the adder; DTSA evaluates aggregate activity using threshold logic; and the output bitstream is produced deterministically according to that thresholding rule. This makes DTSA a deterministic replacement for the MUX-based scaled adder of prior HTC.

A recurrent misconception is to equate “deterministic” with “explicitly exact.” The supplied material supports the conclusion that DTSA is deterministic and more accurate than MUX-based HTC, but it does not explicitly claim that DTSA is exact in the manner of EMBA. The terminology is deliberate: EMBA is labeled Exact, whereas DTSA is labeled Deterministic Threshold-based Scaled Adder. This suggests a distinct exactness–complexity trade-off, although the excerpt does not provide a formal theorem, transfer function, or exact output-value equation.

The provided text is also explicit about what remains unspecified in the excerpt. It does not include the exact threshold formula, closed-form transfer function, unipolar or bipolar output equations, timing equations, accumulation-window rules, or pseudocode for DTSA. Accordingly, any stronger mathematical reconstruction would exceed the documented evidence.

3. Architectural Role in the E-HTC MAC

DTSA is integrated into the E-HTC MAC unit as the accumulation stage following HTC-style multiplication. The relevant framework uses a hybrid representation based on pulse-rate encoding and temporal encoding, so DTSA is not a conventional parallel binary adder inserted into an ordinary datapath; it operates inside a temporal/bitstream computing substrate (Sachdeva et al., 26 Sep 2025).

At the architectural level supported by the source text, the datapath can be summarized as follows. Input operands are represented in temporal or pulse-rate form. Multiplication is then performed in the HTC-style bitstream or temporal domain. The resulting product bitstreams from multiple inputs must be accumulated. DTSA is inserted precisely at that accumulation or scaled-addition stage, replacing the earlier MUX-based method.

The paper further states that the MAC supports both unipolar and bipolar encodings. This is important because it places DTSA in a more general arithmetic context than unipolar-only bitstream adders. However, the supplied material does not disclose the exact bipolar sign-handling strategy. It does not specify whether bipolar values are decomposed into positive and negative streams, whether separate accumulators are used, or whether thresholding occurs before or after sign recombination. The most that can be stated directly is that DTSA operates within a MAC architecture that supports both encoding modes.

The same restraint applies to circuit composition. Because DTSA is characterized as threshold-based, threshold logic is central to its implementation. Beyond that, the excerpt does not enumerate specific hardware blocks such as counters, comparators, registers, FSMs, or dedicated accumulators. A cautious reading therefore treats DTSA as a threshold-logic-based scaled-adder block embedded in the E-HTC MAC, without asserting undocumented microarchitectural details.

Scheme	Summation behavior	Characterization in the supplied text
EMBA	Precise binary accumulation	Explicitly exact
DTSA	Threshold-based scaled addition	Deterministic; not explicitly described as exact
Prior MUX-based HTC	MUX selects among bitstreams	Statistical/approximate scaled addition
CBSC	Counter-based reference	Strong accuracy at higher area/power cost

4. Determinism, Accuracy, and Interpretive Boundaries

The principal significance of DTSA is that it replaces selection-based approximation with a fixed deterministic rule. In prior HTC, the MUX-based scaled adder introduces error because it samples one input stream rather than combining all active inputs deterministically. DTSA addresses this by making each output decision depend on threshold logic rather than on MUX selection, thereby removing or strongly reducing MUX-induced summation error (Sachdeva et al., 26 Sep 2025).

The reported empirical evidence is substantial, but it is reported at the E-HTC framework level rather than as isolated DTSA-only numbers in the supplied excerpt. For a 4×4 MAC in unipolar mode, the abstract states that E-HTC matches the RMSE of state-of-the-art Counter-Based Stochastic Computing (CBSC) MAC, improves accuracy by 94% over MUX-based HTC, and reduces power and area by 23% and 7% compared to MUX-based HTC and 64% and 74% compared to CBSC. In bipolar mode, E-HTC MAC achieves 2.09% RMSE, which is described as an 83% improvement over MUX-based HTC, and approaches CBSC’s 1.40% RMSE while saving 28% and 43% in area and power versus MUX-based HTC and about 76% versus CBSC (Sachdeva et al., 26 Sep 2025).

Expressed numerically, the two RMSE values explicitly given in the excerpt are

$\mathrm{RMSE} = 2.09\%$

for the bipolar E-HTC MAC, and

$\mathrm{RMSE} = 1.40\%$

for the bipolar CBSC reference.

These results support two careful conclusions. The first is factual: deterministic summation in E-HTC, including DTSA, materially improves over MUX-based HTC. The second is interpretive: DTSA should not be casually described as “exact” unless the full paper provides that guarantee. The supplied text supports determinism, repeatability under fixed conditions, and large empirical accuracy gains, but it does not provide formal exactness conditions or deterministic error bounds for DTSA itself.

5. Evaluation in MAC, FIR, and DCT/iDCT Accelerators

The paper validates E-HTC using two accelerators in addition to the MAC primitive: a Finite Impulse Response (FIR) filter and an 8-point Discrete Cosine Transform (DCT)/iDCT engine. These experiments are important because they show that deterministic addition is not merely a local improvement in a micro-benchmark, but also affects application-level signal-processing quality (Sachdeva et al., 26 Sep 2025).

In the FIR experiments, the supplied text states that both E-HTC variants yield PSNR gains of 3–5 dB (30–45% RMSE reduction) while saving 13% power and 3% area. It also reports, relative to CBSC, nearly 64% area reduction and 62% power reduction. In the DCT/iDCT experiments, E-HTC boosts PSNR by 10–13 dB (70–75% RMSE reduction) while saving area and power over both MUX- and CBSC-based designs.

These system-level results are attributable to the E-HTC framework that includes DTSA, but the excerpt explicitly does not separate DTSA and EMBA numerically. That limitation matters for encyclopedia-style characterization. It is accurate to say that DTSA is one of the deterministic summation mechanisms enabling these gains; it is not accurate, on the basis of the supplied excerpt alone, to assign a specific PSNR, RMSE, area, or power figure uniquely to DTSA rather than to E-HTC as a whole.

A plausible implication is that deterministic summation becomes increasingly important as MAC operations are composed into deeper signal-processing pipelines. The paper’s motivation and the reported FIR and DCT/iDCT outcomes are consistent with that interpretation, although the excerpt stops short of presenting a formal error-propagation analysis.

6. Relation to Deterministic Approximate Adder Research

DTSA belongs to a broader class of arithmetic mechanisms that seek deterministic improvement over approximate or probabilistic designs, but its immediate comparison points are specific. Within E-HTC, its closest internal alternatives are MUX-based HTC and EMBA; externally, the paper uses CBSC as a higher-cost reference with strong accuracy (Sachdeva et al., 26 Sep 2025). In a wider approximate-adder context, related work such as “An Approximate Carry Estimating Simultaneous Adder with Rectification” proposes deterministic local decision rules for carry estimation, conditional correction, and tunable accuracy through block partitioning, although it is not a DTSA and does not use temporal/bitstream scaled addition (Bhattacharjya et al., 2020).

That prior work is relevant because it shows a parallel design philosophy: deterministic approximation rather than probabilistic hardware, local decision rules rather than full global propagation, and an explicit trade-off between accuracy and hardware cost. Its architecture divides an $n$-bit adder into $\frac{n}{k}$ $k$-bit blocks, uses a Carry Estimate Unit (CEU) and, in the rectified version, a Propagating Error Rectification Logic (PERL) plus Selection Unit (SU). The selection rule is deterministic,

$$Sel^{i-1}=(A^{i-1}_{k-1}\oplus B^{i-1}_{k-1}).(A^{i-1}_{k-2}\oplus B^{i-1}_{k-2}),$$

and the paper treats it as a fixed ambiguity detector that switches between two carry estimators. It further reports that the carry estimate is correct in 12 of 16 cases, giving

$P(C_{ceu}=C_{radd}) = 12/16 = 3/4,$

and that with PERL the estimated carry error probability becomes

$P(C_{out}\neq C_{radd}) = 1/16.$

The distinction from DTSA is equally important. The approximate simultaneous adder is a deterministic segmented carry-speculation design for binary addition, not a threshold-based scaled adder in a hybrid temporal computing MAC. It has no explicit numeric threshold parameter analogous to what the phrase “threshold-based logic” might suggest for DTSA, and its approximation mechanism is inter-block carry estimation, not temporal scaled summation. Even so, it provides useful prior art for understanding deterministic low-cost arithmetic: local rules can replace expensive exact operations, conditional correction can reduce error, and the resulting area–delay–power trade-offs may be favorable (Bhattacharjya et al., 2020).

A common misconception is therefore to assimilate all deterministic approximate adders under the same category. DTSA is more specifically a deterministic replacement for MUX-based scaled addition inside HTC, whereas deterministic segmented adders such as CESA and CESA-PERL are approximate binary adders based on local carry prediction. The overlap is methodological rather than architectural.

7. Interpretive Summary and Open Technical Unknowns

DTSA is best understood as a deterministic scaled-adder for hybrid temporal computing. Its purpose is to remove the principal accuracy bottleneck of earlier HTC systems: the use of MUX-based scaled addition, which realizes the desired sum only statistically. In E-HTC, DTSA introduces threshold-based logic at the accumulation stage of the MAC, supports unipolar and bipolar encodings, and participates in a framework that reports major improvements in RMSE and PSNR while retaining substantial area and power advantages over CBSC-based designs (Sachdeva et al., 26 Sep 2025).

The most important interpretive boundary is that the supplied excerpt does not disclose the exact DTSA equations, threshold rule, circuit blocks, pseudocode, or timing constraints. For that reason, several questions remain open at the level of the excerpt: whether DTSA is exact under any special conditions, whether thresholding occurs per cycle or across a window, what formal relation links input bitstream rates to output rate in unipolar and bipolar modes, and how threshold logic is instantiated at circuit level.

Within those boundaries, the technically faithful characterization is stable. DTSA is a deterministic threshold-based scaled adder proposed as a replacement for inaccurate MUX-based summation in HTC. It is integrated into the E-HTC MAC, used in FIR and DCT/iDCT accelerators, and associated—through aggregate E-HTC results—with large accuracy gains over MUX-based HTC and markedly lower power and area than CBSC. The supplied evidence supports determinism and substantial empirical benefit; it does not, by itself, support stronger claims about exactness or full formal specification.