Dual-Plane PCB Penning Trap

• The paper demonstrates that a dual-plane PCB Penning trap using mirror-symmetric electrodes eliminates odd multipoles, enabling highly precise single-electron confinement.
• It utilizes orthogonalized tuning of split electrodes to optimize the harmonic axial potential and mitigate amplitude-dependent frequency shifts.
• The architecture paves the way for scalable two-dimensional trap arrays and double-well operation for coherent tunneling in quantum information experiments.

A dual-plane printed-circuit-board Penning trap is a planar Penning-trap architecture in which two patterned electrode planes, typically realized as facing printed-circuit boards, generate the electrostatic confinement while a magnetic field along the common symmetry axis provides radial confinement. In the mirror-symmetric form, the trap center lies between the two planes, so the axial potential inherits exact reflection symmetry and the odd axial multipoles vanish at the midplane. This geometry connects the optimized planar Penning-trap program of Goldman and Gabrielse, the tunable double-well proposal of Ciaramicoli, Marzoli, and Tombesi, and the first demonstration of single-electron trapping and detection in a two-dimensionally scalable dual-plane PCB Penning trap (Goldman et al., 2010, Ciaramicoli et al., 2010, Fang et al., 26 Jun 2026).

1. Architectural concept and historical development

The dual-plane PCB Penning trap is the direct planar realization of the mirror-image Penning-trap geometry: two identical electrode planes face one another along the $z$-axis, each plane lying orthogonal to $z$ and carrying concentric electrodes biased symmetrically. In the analytic treatment of mirror-image planar traps, each plane consists of a central circular electrode and surrounding ring electrodes, while a uniform magnetic field $\mathbf{B} = B \hat{z}$ provides radial confinement exactly as in a standard Penning trap. In the PCB implementation demonstrated for single electrons, the same principle is implemented with two identical 1.5 mm thick gold-plated Rogers 4003C boards separated by a copper spacer ring, with the trap center at the geometric midplane (Ciaramicoli et al., 2010, Fang et al., 26 Jun 2026).

This architecture emerged from a broader effort to adapt Penning trapping from cylindrical or hyperbolic 3D electrodes to chip-fabricable planar structures. Goldman and Gabrielse argued that an electron suspended in a planar Penning trap is a more promising building block for the array of coupled qubits needed for quantum information studies, but also showed that single-plane traps generically suffer from odd multipoles and strong amplitude-dependent axial-frequency shifts unless the geometry is carefully optimized. Their mirror-image and covered-planar constructions were important because they restored much of the symmetry and tuning behavior associated with cylindrical traps while remaining compatible with planar fabrication (Goldman et al., 2010).

The specific descriptor “dual-plane printed-circuit-board Penning trap” refers to the implementation in which the two mirror-symmetric electrode planes are fabricated on standard PCB material and assembled as a stack. In the 2026 single-electron experiment, each plane contains a central circular electrode $e1$ of radius $\rho_1 = 2.00\ \text{mm}$, an annular electrode $e2$ extending to $\rho_2 = 2.85\ \text{mm}$, and a large outer electrode $e3$ extending to $\rho_3 = 25.40\ \text{mm}$. The boards are separated by $2z_0 = 6.0\ \text{mm}$, so the trap center lies $z$0 above and below each PCB. One salient feature is that $z$1 is azimuthally split into two halves, allowing an axial–magnetron coupling drive at $z$2 (Fang et al., 26 Jun 2026).

In a wider Penning-trap context, compact “unitary architecture” traps with embedded NdFeB magnets showed that electric and magnetic structures can be integrated into a single compact assembly, and that radial access can be preserved with symmetric apertures and carefully shaped electrodes. Those traps are not PCB devices, but they established a compact integrated-design logic that is closely aligned with multilayer or dual-plane PCB embodiments (Tan et al., 2012).

2. Electrostatic structure and harmonic optimization

The central electrostatic advantage of the mirror-symmetric dual-plane trap is that the axial potential is symmetric about the midplane. In Goldman and Gabrielse’s mirror-image planar formalism, the on-axis potential is written as

$z$3

which implies

$z$4

at the center. This removes the dominant odd-order anharmonicities that plague single-plane planar traps and makes the device behave much more like a cylindrical trap (Goldman et al., 2010).

For planar Penning traps generally, the axial potential near the equilibrium point is expanded as

$z$5

with $z$6 setting the harmonic curvature and $z$7 encoding anharmonicity. The axial frequency depends on oscillation amplitude through coefficients $z$8, with the leading term

$z$9

Because $\mathbf{B} = B \hat{z}$0 vanishes by symmetry in the mirror-image geometry, the leading shift is controlled primarily by $\mathbf{B} = B \hat{z}$1. Goldman and Gabrielse emphasized conditions such as $\mathbf{B} = B \hat{z}$2, which imply $\mathbf{B} = B \hat{z}$3, and they identified mirror-image geometries that are orthogonalizable: one can tune anharmonicity without shifting the axial frequency (Goldman et al., 2010).

The dual-plane PCB experiment adopts exactly this logic. Near the center, the electrostatic potential is expanded as

$\mathbf{B} = B \hat{z}$4

where $\mathbf{B} = B \hat{z}$5 is applied to the $\mathbf{B} = B \hat{z}$6 electrodes, $\mathbf{B} = B \hat{z}$7 to the split $\mathbf{B} = B \hat{z}$8 electrodes, and $\mathbf{B} = B \hat{z}$9 and the copper spacer are grounded. The axial frequency is

$e1$0

and, because mirror symmetry makes the odd multipoles negligible, the leading amplitude-dependent shift simplifies to

$e1$1

The crucial orthogonality condition is $e1$2: adjusting $e1$3 changes $e1$4 without changing $e1$5, and therefore without shifting $e1$6. For the demonstrated geometry, the raw coefficients include $e1$7, $e1$8, $e1$9, and $\rho_1 = 2.00\ \text{mm}$0; choosing $\rho_1 = 2.00\ \text{mm}$1 gives $\rho_1 = 2.00\ \text{mm}$2 while leaving $\rho_1 = 2.00\ \text{mm}$3 unchanged (Fang et al., 26 Jun 2026).

This electrostatic structure is the main reason the dual-plane PCB trap succeeds where earlier single-plane planar electron traps did not. A plausible implication is that the dual-plane format should be understood not merely as a packaging choice, but as the symmetry-restoring mechanism that makes planar single-electron detection technically viable.

3. Printed-circuit-board realization and experimental operating regime

The single-electron implementation uses two identical PCBs mounted face to face inside a cryogenic Penning-trap apparatus. Each board is aligned mechanically through screw holes, and each contains a central 0.3 mm through-hole for electron loading from below by a field emission point. The two boards are separated by a grounded copper ring spacer, which also defines the mirror symmetry of the electrostatic boundary condition (Fang et al., 26 Jun 2026).

The magnetic field is provided by a superconducting solenoid, JASTEC JMTD‑6T152SS, sweepable from $\rho_1 = 2.00\ \text{mm}$4 to $\rho_1 = 2.00\ \text{mm}$5, with the field oriented along the PCB normal. Most single-electron measurements are performed at $\rho_1 = 2.00\ \text{mm}$6, while low-field studies of magnetron motion extend down to $\rho_1 = 2.00\ \text{mm}$7. From the low-$\rho_1 = 2.00\ \text{mm}$8 dependence of $\rho_1 = 2.00\ \text{mm}$9, the total misalignment between the electrostatic axis and the solenoid field is inferred to be $e2$0 (Fang et al., 26 Jun 2026).

The cryogenic environment is established by housing the trap, field-emission point, and resonator assembly inside a titanium vacuum can cooled to $e2$1 by a pulse-tube cryocooler, JASTEC JMTE-Insert. The experiment does not quote a pressure number, but it reports storage behavior consistent with long single-electron confinement in a cryogenic Penning environment (Fang et al., 26 Jun 2026).

The operating voltages reflect the orthogonalized design strategy. Experimentally, $e2$2 and $e2$3 produce $e2$4 and $e2$5. The slight deviation from the theoretical bias ratio is attributed to machining tolerances and thermal contraction. This is the practical expression of the earlier planar-trap design program: the geometry is chosen so that a single control voltage can null the leading even anharmonicity while preserving the axial curvature (Goldman et al., 2010, Fang et al., 26 Jun 2026).

Although the demonstrated device uses an external superconducting solenoid, compact Penning-trap work with embedded rare-earth permanent magnets established that integrated electric–magnetic architectures can reach central fields around $e2$6 and support storage of highly charged ions with radial access. This suggests that dual-plane PCB Penning traps occupy a broader design space: one branch prioritizes superconducting-field electron experiments; another pursues compact integrated devices with weaker but still usable fields (Tan et al., 2012).

4. Loading, detection, damping, and thermal characterization

Electrons are loaded through the central through-holes by a field-emission point mounted below the trap. During loading, a parametric drive at $e2$7 excites the axial mode nonlinearly. Each captured electron produces a discrete jump in the monitored response amplitude, allowing deterministic loading of an exact number of electrons $e2$8. Once the desired $e2$9 is reached, the field-emission point is turned off (Fang et al., 26 Jun 2026).

Detection is performed on the axial mode through a resonant circuit connected around the top $\rho_2 = 2.85\ \text{mm}$0 electrode. The circuit uses an inductor $\rho_2 = 2.85\ \text{mm}$1 and parasitic capacitance $\rho_2 = 2.85\ \text{mm}$2, giving resonance near $\rho_2 = 2.85\ \text{mm}$3 with quality factor $\rho_2 = 2.85\ \text{mm}$4. The output is fed to a HEMT amplifier, FHX13LG, Fujitsu, typically biased at $\rho_2 = 2.85\ \text{mm}$5. The equivalent parallel resistance is

$\rho_2 = 2.85\ \text{mm}$6

For this geometry, the image-charge pickup constant is $\rho_2 = 2.85\ \text{mm}$7, and the one-electron damping rate is

$\rho_2 = 2.85\ \text{mm}$8

Numerically, this gives $\rho_2 = 2.85\ \text{mm}$9, consistent with the measured $e3$0 from ring-down and $e3$1 from the axial dip linewidth (Fang et al., 26 Jun 2026).

The resistive detection circuit also cools the axial motion. For multiple electrons, the damping is additive,

$e3$2

and the experiment observes this discrete scaling for $e3$3. This number-resolved damping is an operational signature of single-electron sensitivity in a planar architecture (Fang et al., 26 Jun 2026).

Thermal characterization exploits controlled reintroduction of anharmonicity. By detuning $e3$4 by $e3$5, the experiment produces $e3$6, so the axial frequency acquires a thermal distribution through the amplitude dependence. Fitting the resulting asymmetric dip shapes yields

$e3$7

This is substantially above the physical temperature of $e3$8, and the stated interpretation is that HEMT amplifier noise dominates the axial reservoir. The experiment also notes that a detuning of only $e3$9 is needed to produce broadening comparable to the intrinsic linewidth, while the operating point itself has $\rho_3 = 25.40\ \text{mm}$0, indicating that the mirror-symmetric geometry substantially relaxes the precision required of the control voltages (Fang et al., 26 Jun 2026).

A common misconception is that planar Penning traps are intrinsically too anharmonic for single-electron work. The dual-plane PCB result shows that this statement is not correct for mirror-symmetric, orthogonalized geometries: the difficulty was not planarity per se, but the odd multipoles and tuning limitations of single-plane configurations.

5. Double-well operation and axial tunneling in dual-plane geometries

Mirror-image planar Penning traps support not only harmonic axial confinement but also a controllable transition to a double-well potential. Ciaramicoli, Marzoli, and Tombesi analyzed a mirror-image planar trap consisting of two identical electrode planes, each with a central circular electrode and two concentric rings, separated by a distance $\rho_3 = 25.40\ \text{mm}$1. Along the symmetry axis, the exact axial potential in the $\rho_3 = 25.40\ \text{mm}$2 limit is written as

$\rho_3 = 25.40\ \text{mm}$3

with kernel functions expressed as Bessel-function integrals. Near the trap center, the axial potential energy of an electron can be reduced to the quartic form

$\rho_3 = 25.40\ \text{mm}$4

with well separation

$\rho_3 = 25.40\ \text{mm}$5

and barrier height

$\rho_3 = 25.40\ \text{mm}$6

The transition from a single well to a double well occurs when the quadratic coefficient changes sign, and, in the design example, this transition is controlled by varying only the outer-ring voltage $\rho_3 = 25.40\ \text{mm}$7 while keeping $\rho_3 = 25.40\ \text{mm}$8 and $\rho_3 = 25.40\ \text{mm}$9 fixed (Ciaramicoli et al., 2010).

The double-well regime supports coherent tunneling between left- and right-localized axial states. Solving the one-dimensional Schrödinger equation in the quartic potential yields near-degenerate parity doublets $2z_0 = 6.0\ \text{mm}$0, and a state initially localized in one well oscillates between the two wells with tunneling frequency

$2z_0 = 6.0\ \text{mm}$1

For the polynomial double well, the empirical scaling reported is

$2z_0 = 6.0\ \text{mm}$2

so the tunneling frequency scales as $2z_0 = 6.0\ \text{mm}$3 at fixed dimensionless barrier height (Ciaramicoli et al., 2010).

The explicit numerical example is directly relevant to dual-plane microfabricated hardware. For $2z_0 = 6.0\ \text{mm}$4, $2z_0 = 6.0\ \text{mm}$5, $2z_0 = 6.0\ \text{mm}$6, $2z_0 = 6.0\ \text{mm}$7, $2z_0 = 6.0\ \text{mm}$8, and $2z_0 = 6.0\ \text{mm}$9, the trap supports a double well with $z$00 and $z$01. In that case,

$z$02

The authors emphasize that tunneling rates in the range of kHz are achievable even with a trap size of the order of $z$03 microns (Ciaramicoli et al., 2010).

For a dual-plane PCB Penning trap, this does not constitute a demonstrated operating mode in the 2026 experiment, but it is a direct theoretical continuation of the same mirror-symmetric planar geometry. This suggests that a dual-plane PCB device optimized first for harmonic single-electron operation could, in principle, be voltage-tuned into a double-well regime suitable for coherent tunneling studies, provided that the relevant voltages remain stable at the required sub-mV scale.

6. Arrays, coupling mechanisms, and research directions

The dual-plane PCB architecture is explicitly framed as a building block for two-dimensionally scalable Penning-trap arrays. The 2026 experiment emphasizes that the planar electrode pattern can, in principle, be replicated across the PCB surface to form a two-dimensional array, with the rear sides of the boards available for integrated resonators, filters, amplifiers, and coupling structures. The same paper identifies image-charge-mediated coupling between traps as a concrete mechanism, with exchange rate

$z$04

where the same geometry parameters $z$05 and $z$06 that determine damping also set the inter-trap coupling scale (Fang et al., 26 Jun 2026).

For ion arrays, the broader micro-Penning-trap literature provides the many-body normal-mode theory. In scalable two-dimensional arrays of micro-Penning traps, the collective frequencies satisfy the generalized multi-ion invariance theorem

$z$07

and inter-site dipolar exchange rates scale as

$z$08

with $z$09 and $z$10. For $z$11 arrays at $z$12, $z$13, and inter-site distances in the $z$14–$z$15 range, the stated axial exchange rates are $z$16. The same work argues that static trapping fields remove the major power-scaling challenge associated with RF arrays (Jain et al., 2018).

Within the demonstrated single-electron PCB platform, the main identified limitation is low-field magnetron-radius growth for multiple electrons. At $z$17, $z$18, and $z$19, the axial frequency drifts by hundreds of Hz over tens of seconds after magnetron cooling is turned off; the drift reverses sign when the sign of $z$20 is reversed, and it becomes negligible for $z$21 or for $z$22. Varying HEMT bias power or intentionally enlarging the axial amplitude does not significantly change the drift rate, so the stated interpretation is that the effect is collision-induced and that the axial mode is not the main energy reservoir. The paper points instead to cyclotron motion as a likely contributor, although that dependence was not yet systematically controlled (Fang et al., 26 Jun 2026).

Future directions identified for dual-plane PCB Penning traps include cyclotron and spin-flip detection with an integrated magnetic bottle, improved cryogenics and lower-noise amplification to reduce $z$23, vector-magnet or shim-coil alignment of the field to the twin-plane electrostatic axis, and extension from a single trap to arrays. For spin and cyclotron readout, the proposed insertion of iron–cobalt rings would generate $z$24 at $z$25 and $z$26, corresponding to an axial-frequency shift per cyclotron or spin flip of

$z$27

which is well above the measured $z$28 single-electron linewidth (Fang et al., 26 Jun 2026).

Taken together, the literature establishes the dual-plane printed-circuit-board Penning trap as a planar, mirror-symmetric Penning architecture with three distinct attributes: it admits systematic multipole optimization and orthogonalized tuning; it has now been shown experimentally to support deterministic loading, detection, and damping of single electrons; and it furnishes a natural hardware basis for double-well control, image-charge coupling, and eventually two-dimensional arrays for quantum information science (Goldman et al., 2010, Ciaramicoli et al., 2010, Fang et al., 26 Jun 2026)