Gate-Based Reflectometry in Quantum Devices

• Gate-based reflectometry is a radio-frequency technique that embeds a device in a resonator circuit to convert quantum state-dependent admittance changes into detectable amplitude and phase shifts.
• It is applied across diverse semiconductor platforms such as silicon, GaAs, bilayer graphene, and hybrid superconductor devices for precise charge and spin sensing.
• Key experimental implementations focus on impedance engineering, optimal matching conditions, and noise mitigation to achieve high sensitivity and rapid readout.

Gate-based reflectometry is a radio-frequency readout technique in which a gate electrode, or a closely related control node, is embedded in a resonant circuit so that state-dependent changes in device admittance are converted into changes in the amplitude and phase of a reflected carrier. In semiconductor quantum devices, the relevant signal may arise from a quantum capacitance, a tunnel-induced differential capacitance, or a dissipative conductance; in practice, the method has been used for charge sensing, spin readout, finite-bias spectroscopy, defect spectroscopy, and parity-sensitive measurements across silicon, GaAs, bilayer graphene, Ge/Si nanowires, and hybrid superconductor devices (Liu et al., 2020, Crippa et al., 2018, Johmen et al., 2022, Zhang et al., 8 Aug 2025).

1. Fundamental operating principle

The basic one-port description is common across implementations. A resonator with inductance $L$ and total capacitance $C_{\mathrm{tot}}$ has a resonance frequency

$f_0=\frac{1}{2\pi\sqrt{L\,C_{\mathrm{tot}}}},$

and the reflected signal is described by

$$\Gamma(\omega)=\frac{Z(\omega)-Z_0}{Z(\omega)+Z_0},$$

with $Z_0=50\,\Omega$ and $Z(\omega)$ the impedance seen by the feedline (Crippa et al., 2018, 2206.13125, Liu et al., 2020). Depending on the circuit, $C_{\mathrm{tot}}$ may be written as $C_p+C_g$, $C_p+C_q$, or more generally as a sum of parasitic, geometric, and device-dependent terms (Johmen et al., 2022, Hutin et al., 2019).

The device contribution is often expressed as a small-signal admittance

$$Y_{\mathrm{QD}}(\omega)=G+i\omega C_{\mathrm{eff}},$$

where $C_{\mathrm{tot}}$0 captures dissipative transport and $C_{\mathrm{tot}}$1 captures the reactive response (2206.13125). In double quantum dots and related two-level systems, the reactive term is frequently identified with the quantum capacitance. Reported forms include

$C_{\mathrm{tot}}$2

for dispersive readout of hole quantum dots and

$C_{\mathrm{tot}}$3

for the two-level approximation used in hybrid-dot and Kitaev-chain settings (2206.13125, Zhang et al., 8 Aug 2025).

At fixed probe frequency near resonance, a small capacitance change shifts the resonant pole and thereby changes the reflected phase. Several works use the approximation

$C_{\mathrm{tot}}$4

or an equivalent expression in terms of $C_{\mathrm{tot}}$5 (Crippa et al., 2018, Ciriano-Tejel et al., 2020). This formalism makes explicit that gate-based reflectometry is not restricted to purely capacitive sensing: the same reflected tone can respond to tunnel-induced dissipation, device conductance, or mixed reactive-dissipative loading, depending on the relevant tunnel rates and operating point (Crippa et al., 2016, Johmen et al., 2022).

2. Resonator topologies and impedance engineering

A central design problem is to make the device-induced impedance variation visible against parasitic capacitance and line losses. In accumulation-mode Si/SiGe quantum dots, the large parasitic capacitance motivated two mitigation strategies: on-chip modifications such as split-gate geometries and high-kinetic-inductance nanowire inductors, and off-chip PCB tuning using surface-mount inductors, lumped capacitors, and high-value bias resistors (Liu et al., 2020). In undoped AlGaAs/GaAs SETs, the dominant tank capacitance was the top-gate-to-2DEG capacitance, $C_{\mathrm{tot}}$6, while the resonator used $C_{\mathrm{tot}}$7 for 4 K characterization and $C_{\mathrm{tot}}$8 for millikelvin measurements (MacLeod et al., 2013).

Bilayer graphene has led to a distinct capacitance-minimization strategy. In one implementation, an undoped Si wafer removed the global back-gate capacitance and a micrometer-scale graphite flake served as a local back-gate beneath the hBN/BLG stack. The measured parasitic capacitance was $C_{\mathrm{tot}}$9, while the estimated device gate-to-channel capacitance was $f_0=\frac{1}{2\pi\sqrt{L\,C_{\mathrm{tot}}}},$0; with $f_0=\frac{1}{2\pi\sqrt{L\,C_{\mathrm{tot}}}},$1 this gave $f_0=\frac{1}{2\pi\sqrt{L\,C_{\mathrm{tot}}}},$2 (Johmen et al., 2022). A later RFSoC-based BLG experiment used an equivalent series picture in which a coupling capacitor $f_0=\frac{1}{2\pi\sqrt{L\,C_{\mathrm{tot}}}},$3 connected a $f_0=\frac{1}{2\pi\sqrt{L\,C_{\mathrm{tot}}}},$4 source to a resonator formed by $f_0=\frac{1}{2\pi\sqrt{L\,C_{\mathrm{tot}}}},$5, $f_0=\frac{1}{2\pi\sqrt{L\,C_{\mathrm{tot}}}},$6, and a gate-dependent device impedance $f_0=\frac{1}{2\pi\sqrt{L\,C_{\mathrm{tot}}}},$7, with a reported operating point near $f_0=\frac{1}{2\pi\sqrt{L\,C_{\mathrm{tot}}}},$8 and $f_0=\frac{1}{2\pi\sqrt{L\,C_{\mathrm{tot}}}},$9 (Shinozaki et al., 21 Feb 2025).

Varactor-based matching circuits make the resonance frequency and coupling independently tunable. In a p-channel silicon quantum dot at 4.2 K, two GaAs varactors were used: $$\Gamma(\omega)=\frac{Z(\omega)-Z_0}{Z(\omega)+Z_0},$$0 tuned the resonant frequency and $$\Gamma(\omega)=\frac{Z(\omega)-Z_0}{Z(\omega)+Z_0},$$1 tuned the loaded impedance. Best matching was found at $$\Gamma(\omega)=\frac{Z(\omega)-Z_0}{Z(\omega)+Z_0},$$2 and $$\Gamma(\omega)=\frac{Z(\omega)-Z_0}{Z(\omega)+Z_0},$$3, yielding a reflection dip exceeding $$\Gamma(\omega)=\frac{Z(\omega)-Z_0}{Z(\omega)+Z_0},$$4 (Bugu et al., 2021). A later strontium titanate hyperabrupt varactor extended this approach to millikelvin temperatures and magnetic field, with a capacitance range from $$\Gamma(\omega)=\frac{Z(\omega)-Z_0}{Z(\omega)+Z_0},$$5 to $$\Gamma(\omega)=\frac{Z(\omega)-Z_0}{Z(\omega)+Z_0},$$6, stable matching down to $$\Gamma(\omega)=\frac{Z(\omega)-Z_0}{Z(\omega)+Z_0},$$7 and up to $$\Gamma(\omega)=\frac{Z(\omega)-Z_0}{Z(\omega)+Z_0},$$8 in-plane field, and critical coupling near $$\Gamma(\omega)=\frac{Z(\omega)-Z_0}{Z(\omega)+Z_0},$$9 at base temperature (Eggli et al., 2023).

At higher frequency, on-chip superconducting resonators have been used to access compressibility-sensitive capacitance changes. In dual-gated bilayer graphene, an on-chip Nb lumped-element resonator operated near $Z_0=50\,\Omega$0 with loaded quality factor $Z_0=50\,\Omega$1 and an equivalent circuit containing $Z_0=50\,\Omega$2, $Z_0=50\,\Omega$3, spiral shunt capacitance $Z_0=50\,\Omega$4, channel resistance $Z_0=50\,\Omega$5, and a total device capacitance $Z_0=50\,\Omega$6 (An et al., 12 Jun 2026).

3. Physical observables accessible by gate-based reflectometry

The most direct observable is the charge stability diagram. Dual-gate reflectometry in a silicon double quantum dot reconstructed the full honeycomb diagram by monitoring phase shifts from two gate-coupled resonators, and at finite bias the same method detected excited-state lines inside bias triangles (Crippa et al., 2016). In dense $Z_0=50\,\Omega$7 silicon arrays, a single monitored gate was sufficient to establish single-electron occupation in each of the four dots and to detect single-electron movements with high bandwidth through strong capacitive coupling within the array (Ansaloni et al., 2020). In bilayer graphene, RF reflectometry reproduced the same Coulomb-diamond pattern observed in DC transport, with diamond-shaped regions of suppressed response and charging energies reported as $Z_0=50\,\Omega$8–$Z_0=50\,\Omega$9 in one summary and $Z(\omega)$0 in the same dataset’s specific Coulomb-blockade example (Johmen et al., 2022).

Spin readout generally relies on spin-to-charge conversion combined with a reflectometric observable. One route uses a nearby electrometer. In Si MOS split-gate arrays, one split gate was tuned to form a single-electron box tunnel-coupled to a reservoir, and capacitive cross-coupling linked adjacent qubit occupancy to the resonator response; a latched Pauli spin-blockade sequence then produced two well-separated reflectometry levels (Hutin et al., 2019). A second route is direct dispersive spin readout without a reservoir. In a p-type silicon double-gate transistor, the readout gate sensed the phase response associated with spin-selective interdot tunneling at the $Z(\omega)$1 transition, and the appearance of a double-dip in $Z(\omega)$2 at finite magnetic field was identified as a hallmark of spin-dependent dispersive readout (Crippa et al., 2018). Related CMOS experiments used spin-dependent tunneling combined with a low-footprint single-lead quantum-dot charge sensor measured by gate reflectometry, yielding spin-dependent transient phase “blips” during the read interval (Ciriano-Tejel et al., 2020).

Reflectometry also enables parameter extraction beyond charge occupation. In hole double quantum dots, the magnetic-field dependence of the reflected phase at $Z(\omega)$3 was modeled through a Hamiltonian containing site-dependent $Z(\omega)$4-factors $Z(\omega)$5 and $Z(\omega)$6; fitting $Z(\omega)$7 then provided a reflectometry-based method to extract local $Z(\omega)$8-factors (2206.13125). In hybrid quantum-dot–superconductor devices designed as a minimal Kitaev chain, gate reflectometry distinguished elastic cotunneling from crossed-Andreev reflection through the orientation of quantum-capacitance lines in gate space, and in the closed regime it detected parity switching between even and odd ground states (Zhang et al., 8 Aug 2025).

An important corrective to a common simplification is that the method is not limited to intended quantum states. RF reflectometry in silicon SETs revealed quasi-periodic oscillations that persisted in the fully depleted regime; these were modeled as charging of an unintended floating gate in the polycrystalline silicon gate stack, with reported capacitances $Z(\omega)$9 and $C_{\mathrm{tot}}$0 (Villis et al., 2011).

4. Representative material platforms and implementations

The technique has been realized across substantially different device classes and impedance scales.

Platform	Representative resonator parameters	Reported capability
Undoped AlGaAs/GaAs SET (MacLeod et al., 2013)	$C_{\mathrm{tot}}$1–$C_{\mathrm{tot}}$2, $C_{\mathrm{tot}}$3 or $C_{\mathrm{tot}}$4, $C_{\mathrm{tot}}$5–$C_{\mathrm{tot}}$6	Charge sensitivity $C_{\mathrm{tot}}$7
Si MOS split-gate arrays (Hutin et al., 2019)	$C_{\mathrm{tot}}$8–$C_{\mathrm{tot}}$9, $C_p+C_g$0, $C_p+C_g$1	Single-shot spin readout up to $C_p+C_g$2 in $C_p+C_g$3
CMOS hole-spin transistor (Crippa et al., 2018)	$C_p+C_g$4, $C_p+C_g$5, $C_p+C_g$6	Reservoir-free dispersive spin readout and coherent Rabi oscillations
Accumulation-mode Si/SiGe dots (Liu et al., 2020)	Split-gate bandwidth $C_p+C_g$7	Readout fidelity $C_p+C_g$8 for a measurement time of $C_p+C_g$9
BLG with micro-graphite back-gate (Johmen et al., 2022)	$C_p+C_q$0, $C_p+C_q$1, $C_p+C_q$2	Coulomb diamonds and gate-consistent RF/DC response
On-chip superconducting BLG (An et al., 12 Jun 2026)	$C_p+C_q$3, $C_p+C_q$4	Capacitance sensitivity $C_p+C_q$5 per point
Ge/Si nanowire with STO varactor (Eggli et al., 2023)	$C_p+C_q$6, $C_p+C_q$7	Critical coupling at mK and up to $C_p+C_q$8

These examples show that gate-based reflectometry spans both sub-femtofarad quantum-capacitance sensing and regimes dominated by large geometric capacitances. The same formalism has also been applied to large-area silicon carbide transistors, where parasitic capacitances were orders of magnitude larger than in typical quantum devices and the RF response degraded as temperature was lowered because carrier freeze-out changed the effective impedance of the drift region (Zotov et al., 14 May 2026).

5. Performance metrics and experimental operating regimes

Reported performance is strongly architecture-dependent. In accumulation-mode Si/SiGe quantum dots, RF reflectometry enabled charge readout with $C_p+C_q$9 at $$Y_{\mathrm{QD}}(\omega)=G+i\omega C_{\mathrm{eff}},$$0, with an SNR of approximately $$Y_{\mathrm{QD}}(\omega)=G+i\omega C_{\mathrm{eff}},$$1 in $$Y_{\mathrm{QD}}(\omega)=G+i\omega C_{\mathrm{eff}},$$2 at $$Y_{\mathrm{QD}}(\omega)=G+i\omega C_{\mathrm{eff}},$$3 and bandwidth $$Y_{\mathrm{QD}}(\omega)=G+i\omega C_{\mathrm{eff}},$$4 (Liu et al., 2020). In linear Si MOS split-gate arrays, the electrometer-coupled scheme gave readout fidelity in excess of $$Y_{\mathrm{QD}}(\omega)=G+i\omega C_{\mathrm{eff}},$$5 with $$Y_{\mathrm{QD}}(\omega)=G+i\omega C_{\mathrm{eff}},$$6 integration, while a stated SNR of approximately $$Y_{\mathrm{QD}}(\omega)=G+i\omega C_{\mathrm{eff}},$$7 for $$Y_{\mathrm{QD}}(\omega)=G+i\omega C_{\mathrm{eff}},$$8 and $$Y_{\mathrm{QD}}(\omega)=G+i\omega C_{\mathrm{eff}},$$9 corresponded to $C_{\mathrm{tot}}$00; the direct quantum-capacitance scheme yielded fidelities $C_{\mathrm{tot}}$01 in $C_{\mathrm{tot}}$02 (Hutin et al., 2019). Earlier gate-based single-shot spin readout in silicon reported an average fidelity of $C_{\mathrm{tot}}$03, a loaded $C_{\mathrm{tot}}$04, and an optimal dispersive spin-readout time of about $C_{\mathrm{tot}}$05 (West et al., 2018).

Charge sensitivity has also been quantified directly. The undoped GaAs SET yielded $C_{\mathrm{tot}}$06 at $C_{\mathrm{tot}}$07 resolution bandwidth, $C_{\mathrm{tot}}$08, and a $C_{\mathrm{tot}}$09 gate excitation at $C_{\mathrm{tot}}$10 (MacLeod et al., 2013). The p-channel silicon quantum dot with dual varactors reported $C_{\mathrm{tot}}$11, SNR $C_{\mathrm{tot}}$12 for $C_{\mathrm{tot}}$13 at $C_{\mathrm{tot}}$14, and a resonance range of $C_{\mathrm{tot}}$15–$C_{\mathrm{tot}}$16 (Bugu et al., 2021). In superconducting GHz BLG reflectometry, the measured resonance shift $C_{\mathrm{tot}}$17 near the gap corresponded to $C_{\mathrm{tot}}$18, while the resonance-tracking uncertainty implied a capacitance sensitivity $C_{\mathrm{tot}}$19 per point (An et al., 12 Jun 2026).

Matching conditions are often the decisive factor. In BLG RFSoC reflectometry, the resonator matching conductance was estimated as $C_{\mathrm{tot}}$20, but the device remained at $C_{\mathrm{tot}}$21, so the experiment operated off-match with reduced sensitivity by roughly a factor of two (Shinozaki et al., 21 Feb 2025). In the micro-graphite BLG implementation, the reflection coefficient was most sensitive in the pinch-off regime $C_{\mathrm{tot}}$22 where $C_{\mathrm{tot}}$23 crossed zero (Johmen et al., 2022).

6. Limitations, error mechanisms, and scaling directions

Several limitations recur across platforms. Parasitic capacitance and RF leakage flatten the reflectometry response by shunting current away from the device. This is explicit in large-top-gate silicon nanostructures, where gate leakage dominated for carrier frequencies well above $C_{\mathrm{tot}}$24 in one device, and in large-area SiC transistors, where large gate-source and gate-drain capacitances together with drift-region freeze-out caused the RF response to vanish below about $C_{\mathrm{tot}}$25 even though DC MOSFET operation persisted (Bugu et al., 2021, Zotov et al., 14 May 2026). These observations directly motivate local-gate layouts, compact routing, added decoupling capacitance, and explicit source/drain RF engineering.

Noise mechanisms are equally central. In BLG source-connected reflectometry, the measured noise spectrum was described by

$C_{\mathrm{tot}}$26

and the flicker-noise amplitude $C_{\mathrm{tot}}$27 correlated with $C_{\mathrm{tot}}$28, indicating that charge noise near the BLG limited sensitivity (Johmen et al., 2022). A broader theoretical treatment showed that slow charge noise broadens the state-conditioned reflectance distributions, while overdriving can saturate the parametric-capacitance contrast for charge and spin qubits and create resonance-like error peaks through probe-induced multiphoton transitions (Maman et al., 2020).

A second common misconception is that the technique necessarily requires a separate charge sensor or a reservoir-coupled geometry. Multiple experiments contradict that simplification. Reservoir-free direct dispersive sensing was demonstrated in Si MOS split-gate arrays, the CMOS hole-spin device explicitly emphasized readout without coupling to a Fermi reservoir, and dense silicon arrays used within-array sensing without adjacent electron reservoirs (Hutin et al., 2019, Crippa et al., 2018, Ansaloni et al., 2020). This suggests that the architectural value of gate-based reflectometry lies not only in bandwidth, but also in reduction of device overhead.

Current scaling directions are correspondingly focused on integrated matching, multiplexing, and richer state discrimination. Frequency-division multiplexing of multiple gate resonators is an explicit design goal in silicon spin-qubit architectures (Crippa et al., 2018, Hutin et al., 2019). RFSoC-based BLG reflectometry addresses measurement-stack complexity by moving signal generation and demodulation onto scalable digital hardware, although the reported device remained limited by off-match operation (Shinozaki et al., 21 Feb 2025). Theoretical work on paired spin qubits extends the same reflectometric principle from binary spin-to-charge conversion to four-state discrimination through state-dependent quantum capacitances, with a proposed single-measurement protocol in the Pauli-spin-blockade regime (Sen et al., 8 Mar 2026). In hybrid-dot–superconductor devices, gate reflectometry has already been shown to resolve parity dynamics in the absence of transport (Zhang et al., 8 Aug 2025).

Across these developments, gate-based reflectometry appears less as a single circuit recipe than as a family of impedance-transduction methods: the resonator may be gate-coupled, source-connected, dual-gated, varactor-matched, superconducting, or frequency-multiplexed, but the central object remains the same—a state-dependent admittance encoded in the complex reflection coefficient.