Dual-Gate Architecture: Principles & Applications

• Dual-gate architecture is a family of electrostatic designs using two independent gates to separately control channel conduction, contact properties, and carrier density.
• It decouples device functions by independently tuning parameters like threshold voltage, displacement field, and carrier confinement for improved performance.
• Applications span CMOS, reconfigurable logic, quantum dots, topological films, and spintronic devices, offering enhanced versatility and control.

Dual-gate architecture denotes a device topology in which two independently addressable gates act on the same active region or on distinct regions of a device, so that channel control, contact electrostatics, carrier density, disorder, threshold voltage, displacement field, or inter-dot coupling can be tuned separately or jointly. The concept appears in several non-equivalent geometries: stacked front/back gates in SOI and 2D FETs, localized dual gates that define voltage-tunable quantum dots, coplanar in-plane gates coupled through proton-conducting or solid-state electrolytes, and dual-material double-gate structures in which one gate electrode is itself segmented into two work functions. Across these realizations, the second gate is used to impose a second electrostatic boundary condition, to reshape injection barriers, or to control a vertical electric field that a single-gate device cannot independently set (Krauss et al., 2014, Chen et al., 2018, Bai et al., 2024, Reddy et al., 2010).

1. Architectural forms and definitional scope

Dual-gate architecture is not a single device layout but a family of electrostatic designs. In a planar dopant-free SOI FET, a long back gate biases an undoped body to accumulate either electrons or holes at the buried oxide interface, while a localized front control gate in the middle of the channel acts as a depletion-mode element that sets threshold and suppresses leakage (Krauss et al., 2014). In monolayer MoS$_2$, a symmetric dual-gate structure with independently addressable back and top gates was explicitly constructed so that the back gate modulates the semiconductor under the channel and under the source/drain contacts, whereas the top gate primarily modulates the channel and only weakly the contact regions (Ravel et al., 12 Nov 2025). In PEDOT:PSS OECTs, two coplanar PEDOT:PSS gates share the same solid-state electrolyte volume, and the overall network is described as two parallel gate capacitors in series with the channel capacitor (Tseng et al., 2023).

The same designation also covers architectures in which the gates are spatially localized and play quantum-functional rather than classical transistor roles. In GaAs nanowire devices, replacing a single gate by two localized gates creates two voltage-tunable quantum dots beneath the gates, with independently tunable detuning and tunnel coupling for room-temperature charge-qubit operation (Paul et al., 2023, Chowdhury et al., 2021). In topological thin films such as MnBi$_2$Te$_4$, the dual-gate structure is required because both top and bottom surface states must be tuned simultaneously, and because the device must control not only carrier density but also a vertical displacement field across the film (Bai et al., 2024). In bilayer Cr$_2$SeO tunnel junctions, each electrode region is controlled by its own top and bottom gate pair so that the sign of the vertical electric field can be set independently on the left and right electrodes (Gao et al., 29 Dec 2025).

A useful unifying description is therefore electrostatic partitioning: one gate may control the channel while the other controls contacts, one may set total density while the other changes confinement, or one may define a source-side tunneling junction while the other suppresses drain-side leakage. This suggests that “dual-gate” is best treated as a functional designation rather than a fixed geometry.

2. Electrostatic principles and transport formalisms

The common foundation is coupled electrostatics. In the undoped planar SOI FET, Poisson’s equation is written as

$\nabla \cdot (\varepsilon \nabla \phi) = -\rho,$

and the body potential under dual-gate bias is approximated by

$$\phi_{\mathrm{body}} \approx \alpha_f V_{Gf} + \alpha_b V_{Gb} + \phi_0,$$

with coupling factors determined by the front- and back-gate capacitances (Krauss et al., 2014). In dual-gated MnBi$_2$Te$_4$, the same logic is re-expressed in terms of carrier density and displacement field,

$$n = (n_T + n_B) + n_0, \qquad D = \frac{-e n_T + e n_B}{\varepsilon_0} + D_0,$$

so that dual gating can move along trajectories of nearly constant $\Delta n$ while varying $_2$0 (Bai et al., 2024). At the LAO/STO interface, the two gates impose different boundary conditions on an asymmetric quantum well: the top electric-double-layer gate primarily sets the near-interface field and the back gate lifts or lowers the far-side boundary, thereby redistributing the weakly confined electron tail without equivalently changing the near-interface dielectric collapse (Chen et al., 2018).

Transport models are correspondingly platform-specific. The dopant-free SOI FET was analyzed with 2D Silvaco Atlas drift-diffusion plus thermionic emission, thermionic-field emission, and direct tunneling at the Schottky contacts (Krauss et al., 2014). The LaAlO$_2$1/SrTiO$_2$2 heterointerface used a self-consistent Poisson–Schrödinger model and a two-carrier parameterization of magnetotransport, with high-mobility electrons deeper in STO and low-mobility electrons strongly confined near the disordered interface (Chen et al., 2018). Quantum nanowire devices used Schrödinger–Poisson self-consistency coupled to NEGF or Landauer transport,

$_2$3

while the effective qubit Hamiltonian reduces to

$_2$4

for the two localized dot states (Paul et al., 2023, Chowdhury et al., 2021).

A persistent theme is that the second gate does not simply add capacitance. In oxide interfaces it changes confinement and disorder independently from total density; in topological films it separates carrier-density control from displacement-field control; and in reconfigurable Schottky devices it decouples polarity selection from current-flow control (Krauss et al., 2014, Chen et al., 2018, Bai et al., 2024).

3. Reconfigurable transistors, logic devices, and classical double-gate MOSFETs

In classical scaled transistors, the dual-gate architecture was adopted to strengthen electrostatic control and suppress short-channel effects. The dual-material double-gate SOI MOSFET places two front-gate materials with different work functions along the channel, producing a perceivable step in the surface potential profile that screens the drain potential. The reported consequence is simultaneous increase in transconductance and decrease in drain conductance relative to the corresponding DG structure (Reddy et al., 2010). A more recent silicon DMDG source-pocket TFET with homogeneous HfO$_2$5 gate dielectric used the same field-engineering principle in a BTBT device. In that study, the source pocket produced a 6.7x higher ON current and a 1.7x lower subthreshold swing than a pocket-less device, while dual-material gates added a 45% ON-current increase and a 59% ON/OFF improvement over the single-material pocket device; the optimized structure reached $_2$6 A/$_2$7m, $_2$8 A/$_2$9m, $_4$0, and $_4$1 mV/decade (Fariha et al., 10 Jun 2025).

In reconfigurable devices, dual gating separates polarity programming from channel switching. The planar dopant-free SOI FET with midgap Schottky source/drain contacts uses a long back gate to accumulate electrons or holes at the BOX interface and thereby select n-type or p-type operation on demand, while a localized dual-metal front gate shapes the central barrier. Silvaco Atlas simulations reported on/off ratios up to about 11 decades, leakage around 1 aA/$_4$2m, threshold shifts of approximately 100 mV per volt of $_4$3, and a four-orders-of-magnitude reduction of crossing current near $_4$4 mV when the front gate was split into $_4$5 eV and $_4$6 eV segments (Krauss et al., 2014). In silicon nanowire RFETs with Ni-silicide Schottky contacts, the same reconfigurable idea appears in the program-gate-at-drain and program-gate-at-source configurations: PGAD suppresses ambipolar operation but has Schottky-limited switching, whereas PGAS gives MOSFET-like switching at the cost of strongly non-linear low-bias output characteristics (Sun et al., 2021).

Ambipolar 2D logic exploits dual-gate polarity control in a different way. In WSe$_4$7 thin-film transistors with asymmetric contacts and hBN encapsulation, the control gate modulates the channel and the polarity gate modulates the Schottky barriers at the contacts. Reported transfer metrics include $_4$8 fA and on/off $_4$9 in p-type mode, $_2$0 fA and on/off $_2$1 in n-type mode, and subthreshold swings of 62 and 63 mV/dec; the same platform was used to demonstrate cascadable inverters, XOR, NAND, NOR, and buffers in a unified 0–4 V range, as well as VT-drop logic with reduced transistor count (Li et al., 2023). In MoS$_2$2 dual-gate FETs with symmetric high-$_2$3 HfO$_2$4 dielectrics, the extra gate provided threshold and subthreshold control in multilayer channels, leading to monolayer current density $_2$5A/$_2$6m, $_2$7 mV/dec for 5 nm thickness, $_2$8 on/off for 10 nm thickness, and a 1T1C DRAM retention time of 1260 ms (Liao et al., 2019).

4. Quantum, topological, and spintronic realizations

Dual-gate architectures are central to room-temperature charge-qubit proposals based on nanowire FETs. In GaAs nanowires with $_2$9–10 nm, $\nabla \cdot (\varepsilon \nabla \phi) = -\rho,$0 nm, and $\nabla \cdot (\varepsilon \nabla \phi) = -\rho,$1–8 nm, the two gates define left and right voltage-tunable quantum dots, $\nabla \cdot (\varepsilon \nabla \phi) = -\rho,$2 and $\nabla \cdot (\varepsilon \nabla \phi) = -\rho,$3. Differential control of $\nabla \cdot (\varepsilon \nabla \phi) = -\rho,$4 and $\nabla \cdot (\varepsilon \nabla \phi) = -\rho,$5 tunes detuning $\nabla \cdot (\varepsilon \nabla \phi) = -\rho,$6, while geometry and gate bias tune the tunnel coupling $\nabla \cdot (\varepsilon \nabla \phi) = -\rho,$7. The later study reported $\nabla \cdot (\varepsilon \nabla \phi) = -\rho,$8 meV for $\nabla \cdot (\varepsilon \nabla \phi) = -\rho,$9 nm and $$\phi_{\mathrm{body}} \approx \alpha_f V_{Gf} + \alpha_b V_{Gb} + \phi_0,$$0 nm, $$\phi_{\mathrm{body}} \approx \alpha_f V_{Gf} + \alpha_b V_{Gb} + \phi_0,$$1 meV for $$\phi_{\mathrm{body}} \approx \alpha_f V_{Gf} + \alpha_b V_{Gb} + \phi_0,$$2 nm and $$\phi_{\mathrm{body}} \approx \alpha_f V_{Gf} + \alpha_b V_{Gb} + \phi_0,$$3 nm, and $$\phi_{\mathrm{body}} \approx \alpha_f V_{Gf} + \alpha_b V_{Gb} + \phi_0,$$4 meV for $$\phi_{\mathrm{body}} \approx \alpha_f V_{Gf} + \alpha_b V_{Gb} + \phi_0,$$5 nm and $$\phi_{\mathrm{body}} \approx \alpha_f V_{Gf} + \alpha_b V_{Gb} + \phi_0,$$6 nm; dephasing times ranged from $$\phi_{\mathrm{body}} \approx \alpha_f V_{Gf} + \alpha_b V_{Gb} + \phi_0,$$7 ns at $$\phi_{\mathrm{body}} \approx \alpha_f V_{Gf} + \alpha_b V_{Gb} + \phi_0,$$8 nm, $$\phi_{\mathrm{body}} \approx \alpha_f V_{Gf} + \alpha_b V_{Gb} + \phi_0,$$9 nm to $_2$0 ns at $_2$1 nm, $_2$2 nm (Paul et al., 2023). The earlier NEGF study on the same concept reported a coherent oscillation frequency of $_2$3 MHz, a characteristic decay time of $_2$4 ns, and pA-order pulse-current readout under a small drain bias (Chowdhury et al., 2021).

In topological matter, dual gating is used to tune both surfaces of a thin film and to apply a controllable vertical electric field. Dual-gated MnBi$_2$5Te$_2$6 thin films grown on SrTiO$_2$7(111) used the substrate as the bottom-gate dielectric and a 40 nm AlO$_2$8 layer as the top-gate dielectric. At $_2$9 mK and $_4$0 T, the Hall and longitudinal resistivities showed inversed gate-voltage dependence for both top- and bottom-gate sweeps, which was identified as the key evidence for dissipationless edge transport in the Chern-insulator phase. The maximum Hall resistivity reached only $_4$1, and the paper attributed the incomplete quantization to a high density of bulk carriers introduced by secondary phases (Bai et al., 2024).

A more explicitly spintronic dual-gate concept appears in the bilayer Cr$_4$2SeO altermagnetic tunnel junction. There, each electrode region is gated from top and bottom so that the sign of $_4$3 can be set independently. The bilayer remains semiconducting at small $_4$4 but becomes metallic at $_4$5 V/\AA; reversing the field flips the valley spin polarization without rotating the Néel vector. The low-resistance state corresponds to equal $_4$6 signs on both electrodes and the high-resistance state to opposite signs, with reported zero-bias TMR up to $_4$7 at $_4$8 V and still $_4$9 at $$n = (n_T + n_B) + n_0, \qquad D = \frac{-e n_T + e n_B}{\varepsilon_0} + D_0,$$0 V (Gao et al., 29 Dec 2025).

5. Optoelectronic, ionic, and correlated-electron systems

In phototransistors, dual gating is frequently used to separate gain control from dark-current control. A vertical dual-gate multilayer WSe$$n = (n_T + n_B) + n_0, \qquad D = \frac{-e n_T + e n_B}{\varepsilon_0} + D_0,$$1 phototransistor used opposite dual-gating to create a p-type channel near one interface and an n-type channel near the other, effectively forming a vertical p–n homojunction inside the same flake. Under $$n = (n_T + n_B) + n_0, \qquad D = \frac{-e n_T + e n_B}{\varepsilon_0} + D_0,$$2 V, $$n = (n_T + n_B) + n_0, \qquad D = \frac{-e n_T + e n_B}{\varepsilon_0} + D_0,$$3 V, and $$n = (n_T + n_B) + n_0, \qquad D = \frac{-e n_T + e n_B}{\varepsilon_0} + D_0,$$4 V, the device showed a linear photoresponse with $$n = (n_T + n_B) + n_0, \qquad D = \frac{-e n_T + e n_B}{\varepsilon_0} + D_0,$$5 A/W over $$n = (n_T + n_B) + n_0, \qquad D = \frac{-e n_T + e n_B}{\varepsilon_0} + D_0,$$6 to $$n = (n_T + n_B) + n_0, \qquad D = \frac{-e n_T + e n_B}{\varepsilon_0} + D_0,$$7 mW cm$$n = (n_T + n_B) + n_0, \qquad D = \frac{-e n_T + e n_B}{\varepsilon_0} + D_0,$$8, a detectivity of $$n = (n_T + n_B) + n_0, \qquad D = \frac{-e n_T + e n_B}{\varepsilon_0} + D_0,$$9 Jones, and NEP $\Delta n$0 fW Hz$\Delta n$1 in the linear regime (Xu et al., 2022). A related MoS$\Delta n$2 dual-gate phototransistor used the interface coupling effect: a negative top-gate voltage and positive back-gate voltage trapped photogenerated holes near the top interface while electrons conducted near the bottom interface. Several devices with thickness 2.5–6.5 nm achieved responsivity of $\Delta n$3 A/W and detectivity of $\Delta n$4 Jones at low $\Delta n$5, while more negative $\Delta n$6 reduced the rise time from 11.9 s to 8.3 s and the fall time from 76.2 s to 46.4 s (Liao et al., 2019).

In correlated oxides, the second gate enables a decomposition that is difficult to achieve in conventional semiconductors. At the LaAlO$\Delta n$7/SrTiO$\Delta n$8 interface, a hybrid liquid/solid dual-gate geometry provided an extra degree of freedom to strongly modify the electron confinement profile and thus the strength of interfacial scattering, independently from the carrier density. The nonlinear Hall effect, the redistribution between high-mobility and low-mobility carriers, and the wide tunable range of density and disorder were all interpreted through a Poisson–Schrödinger subband model with field-dependent STO permittivity (Chen et al., 2018).

Ionic and electrochemical devices use dual gating to tune threshold voltage and operating mode directly during operation. PEDOT:PSS dual-gate OECTs with a shared solid-state electrolyte showed a threshold shift

$\Delta n$9

so that the degree of threshold tuning scaled linearly with gate capacitance and, for fixed thickness, with gate area. The devices could be pushed to accumulation-mode operation, which the work used to simplify complementary inverter design (Tseng et al., 2023). In paper electronics, self-aligned junctionless ITO channels with chitosan proton-conductor gating operated below 1.5 V, tuned $_2$00 from $_2$01 V to $_2$02 V as the second in-plane gate was swept from $_2$03 V to $_2$04 V, and implemented an OR logic gate in a single device (Dou et al., 2012).

6. Design trade-offs, interpretive issues, and scaling constraints

Several studies show that the second gate can primarily act on contacts, disorder, or displacement field rather than simply duplicate channel control. The clearest quantitative example is the symmetric monolayer MoS$_2$05 study of contact gating. There, the back gate inherently included full contact gating while the top gate largely did not, and the comparison defined off- and on-state contact-gating factors. The reported effect was a 2x enhancement in on-state performance in long-channel devices, a 5x increase in on-state performance at 50 nm channel and 30 nm contact length, and a 70% reduction in transfer length when contact gating was present (Ravel et al., 12 Nov 2025). This directly complicates interpretation of record-performance 2D FETs that rely on overlapping back-gate geometries.

The benefits of dual gating are therefore coupled to stringent materials and process constraints. In the dopant-free SOI reconfigurable transistor, leakage suppression degraded dramatically when the front-gate recess channel height increased from 10 nm to 30 nm, changing leakage from $_2$06 aA/$_2$07m to $_2$08 nA/$_2$09m and reducing on/off from $_2$10 decades to $_2$11 decades (Krauss et al., 2014). In the DMDG-SP TFET, the design choice of a homogeneous HfO$_2$12 gate dielectric was explicitly motivated by the fabrication complexity and reliability concerns of heterogeneous gate dielectrics, while still preserving strong field engineering through the dual-material gate and the source pocket (Fariha et al., 10 Jun 2025). In dual-gated MoS$_2$13 MOSFETs, ALD Al$_2$14O$_2$15 nucleated uniformly on MoS$_2$16 at $_2$17C but showed poor coverage at $_2$18C, emphasizing that gate-stack quality can determine whether the architecture is practically realizable (Liu et al., 2011).

A second recurring issue is asymmetry. Dual-gate systems are often described as symmetric, but several papers show deliberately broken symmetry: one gate may sit closer to the source to favor initialization of a left dot, one gate may be screened from contact regions by source/drain metals, or one gate segment may be assigned a lower work function to intensify source-side tunneling while the other suppresses drain-side ambipolarity (Paul et al., 2023, Ravel et al., 12 Nov 2025, Fariha et al., 10 Jun 2025). This suggests that the most consequential design variable is frequently not the existence of two gates per se, but the deliberate non-equivalence of their electrostatic roles.

In that sense, dual-gate architecture is less a single device class than a general strategy for decoupling functions that are entangled in single-gate structures: polarity and conduction, density and disorder, contacts and channel, carrier density and displacement field, gain and linearity, or qubit detuning and tunnel coupling. The breadth of reported implementations indicates that the architecture remains relevant from nanoscale CMOS and reconfigurable logic to optoelectronics, correlated oxides, topological transport, and spintronic tunnel junctions (Li et al., 2023, Xu et al., 2022, Chen et al., 2018, Bai et al., 2024, Gao et al., 29 Dec 2025).