Single-Layer Depletion Fine Gates in Quantum Devices

• Single-layer depletion fine gates are nanostructured architectures that use localized electrostatic depletion via a single patterned gate layer or built-in charge to control carrier density.
• They simplify fabrication by eliminating complex multilayer alignments, while introducing challenges such as lateral cross-coupling and threshold variability.
• Experimental implementations in graphene, Si/SiGe, InSb, GaAs, and all-Si systems show tunable quantum dot behavior with trade-offs in bias windows and precise dielectric engineering.

Searching arXiv for the cited papers and closely related work on single-layer depletion/fine-gate architectures. “Single-layer depletion fine gates” (Editor’s term) denotes a family of nanostructure architectures in which carrier gases, tunnel barriers, quantum dots, or local band-edge profiles are defined primarily through depletion using a single patterned gate layer, in-plane gates patterned from the active material itself, or localized depletion charge, rather than vertically stacked overlapping gate levels. In the literature surveyed here, this includes single-layer graphene gates carved from the device sheet, single-layer Al finger gates that deplete an induced two-dimensional hole gas in intrinsic Si, single-metal-layer gates in undoped Si/SiGe quantum dots, single insulated depletion gates for InSb two-dimensional electron gases, local screen gates beneath a global top gate in GaAs/AlGaAs, and heavily doped Si depletion regions used as built-in all-Si ultra-fine gates in GAAFET-like structures (Wang et al., 2011, Amitonov et al., 2017, Lu et al., 2016, Uddin et al., 2013, Bachsoliani et al., 2017, Xu et al., 23 Jan 2025).

1. Conceptual scope and electrostatic basis

Across these platforms, the unifying operation is local modulation of carrier density by electrostatic depletion. The control variable may be a lateral gate voltage, a global back gate, a top gate screened by local metal features, or a built-in fixed or depletion charge. The relevant models are correspondingly capacitive or Poisson-based. In intrinsic Si depletion-mode dots, the oxide/semiconductor stack is described by

$\nabla\cdot[\varepsilon(x)\nabla\psi(x)]=-\rho(x),$

with a surface-potential criterion

$\psi_s \approx (Q_f + Q_{it})/C_{ox},$

and a fixed-charge-induced threshold shift

$V_{th}\simeq -Q_f/C_{ox}.$

In undoped Si/SiGe, the induced electron density above threshold is modeled as

$n_s=(C_g/e)(V_G-V_{th}).$

In InSb, the depleted 2DEG is treated with a series-capacitance model,

$n_s(V_g)\simeq (C_{tot}/e)(V_g-V_{th}),$

while the GaAs/AlGaAs screen-gate architecture uses

$$n = (C_s/e)(V_s - V_s^d) + (\alpha C_t^0/e)(V_t - V_{th}),$$

with a screening factor $\alpha \simeq 1/11.7$ under the screen gate (Amitonov et al., 2017, Lu et al., 2016, Uddin et al., 2013, Bachsoliani et al., 2017).

These formulations differ in materials, sign conventions, and whether the depleted system is electron-like or hole-like, but they all reduce fine-gate action to local control of electrochemical potential and barrier height. A recurring result is that single-layer architectures simplify fabrication while shifting complexity into lateral cross-coupling, threshold engineering, and disorder control.

Platform	Fine-gate realization	Reported characteristic scales
Single-layer graphene	Seven in-plane graphene plunger gates in the same sheet	30–35 nm constrictions; two 100 nm dots; $E_M$ tunable from $<1$ meV to $\sim4$ meV
Intrinsic Si	Single Al gate layer depleting a fixed-charge-induced 2DHG	50–100 nm finger widths; 60–80 nm spacing; $\psi_s \approx (Q_f + Q_{it})/C_{ox},$0 meV or $\psi_s \approx (Q_f + Q_{it})/C_{ox},$1–$\psi_s \approx (Q_f + Q_{it})/C_{ox},$2 meV
Undoped Si/Si$\psi_s \approx (Q_f + Q_{it})/C_{ox},$3Ge$\psi_s \approx (Q_f + Q_{it})/C_{ox},$4	Single metal finger-gate layer	Narrowest channel $\psi_s \approx (Q_f + Q_{it})/C_{ox},$5 nm; single-dot to double-dot transition with $\psi_s \approx (Q_f + Q_{it})/C_{ox},$6
InSb 2DEG	Single Al$\psi_s \approx (Q_f + Q_{it})/C_{ox},$7O$\psi_s \approx (Q_f + Q_{it})/C_{ox},$8-insulated top depletion gate	Full depletion at $\psi_s \approx (Q_f + Q_{it})/C_{ox},$9 V; hysteresis $V_{th}\simeq -Q_f/C_{ox}.$0 mV
GaAs/AlGaAs 2DES	Local screen gates below a global top gate	Screen-gate width $V_{th}\simeq -Q_f/C_{ox}.$1–300 nm; sub-100 nm depletion tails; $V_{th}\simeq -Q_f/C_{ox}.$2 V

2. In-plane graphene fine gates

In the single-layer graphene parallel-double-dot device, the fine depletion gates are not deposited metal lines but narrow graphene fingers carved from the same single-layer sheet and placed within 30–100 nm of the dot islands. The substrate is highly $V_{th}\simeq -Q_f/C_{ox}.$3-doped Si, used as a global back gate, with 100 nm thermal SiO$V_{th}\simeq -Q_f/C_{ox}.$4. A single EBL-plus-RIE step defines two 100 nm-diameter dot islands, four 30 nm-wide constrictions that act as tunnel barriers to source and drain, a 35 nm-wide constriction between the dots, and seven in-plane plunger gates. The gate set comprises $V_{th}\simeq -Q_f/C_{ox}.$5, $V_{th}\simeq -Q_f/C_{ox}.$6, $V_{th}\simeq -Q_f/C_{ox}.$7, $V_{th}\simeq -Q_f/C_{ox}.$8, and $V_{th}\simeq -Q_f/C_{ox}.$9. After O$n_s=(C_g/e)(V_G-V_{th}).$0/Ar RIE, Ti/Au leads and contact pads of 2 nm/50 nm are deposited by a second EBL and e-beam evaporation (Wang et al., 2011).

The depletion mechanism is explicitly electrostatic. A negative voltage on a graphene gate finger, for example $n_s=(C_g/e)(V_G-V_{th}).$1, reduces the local charge-carrier density underneath by shifting the local Fermi level toward the Dirac point. When graphene under a 30–35 nm constriction is depleted, a tunnel barrier forms. The two 100 nm disks between constrictions then act as zero-dimensional islands. A special feature is the middle gate $n_s=(C_g/e)(V_G-V_{th}).$2, which is carried on an overexposed-PMMA bridge above the graphene plane so that it can be biased independently without contacting the drain graphene region.

Transport through the structure exhibits a honeycomb charge-stability diagram from which the full capacitance model is extracted. Reported values include $n_s=(C_g/e)(V_G-V_{th}).$3 V, $n_s=(C_g/e)(V_G-V_{th}).$4 V, $n_s=(C_g/e)(V_G-V_{th}).$5 V, and $n_s=(C_g/e)(V_G-V_{th}).$6 V at $n_s=(C_g/e)(V_G-V_{th}).$7. These give $n_s=(C_g/e)(V_G-V_{th}).$8 aF and $n_s=(C_g/e)(V_G-V_{th}).$9 aF, lever arms $n_s(V_g)\simeq (C_{tot}/e)(V_g-V_{th}),$0 and $n_s(V_g)\simeq (C_{tot}/e)(V_g-V_{th}),$1, total dot capacitances $n_s(V_g)\simeq (C_{tot}/e)(V_g-V_{th}),$2 aF and $n_s(V_g)\simeq (C_{tot}/e)(V_g-V_{th}),$3 aF, charging energies $n_s(V_g)\simeq (C_{tot}/e)(V_g-V_{th}),$4 meV and $n_s(V_g)\simeq (C_{tot}/e)(V_g-V_{th}),$5 meV, and an interdot coupling energy $n_s(V_g)\simeq (C_{tot}/e)(V_g-V_{th}),$6 meV from $n_s(V_g)\simeq (C_{tot}/e)(V_g-V_{th}),$7 V. The electrochemical potentials are written as

$n_s(V_g)\simeq (C_{tot}/e)(V_g-V_{th}),$8

$n_s(V_g)\simeq (C_{tot}/e)(V_g-V_{th}),$9

with the honeycomb boundaries given by $$n = (C_s/e)(V_s - V_s^d) + (\alpha C_t^0/e)(V_t - V_{th}),$$0 or $$n = (C_s/e)(V_s - V_s^d) + (\alpha C_t^0/e)(V_t - V_{th}),$$1.

This graphene realization is important because it shows that “fine gates” need not be metallic. The same material layer can host the islands, the tunnel barriers, and the lateral gates. It also shows that single-layer operation does not preclude wide tunability: the back gate moves the system from hole transport to electron transport, and $$n = (C_s/e)(V_s - V_s^d) + (\alpha C_t^0/e)(V_t - V_{th}),$$2 tunes $$n = (C_s/e)(V_s - V_s^d) + (\alpha C_t^0/e)(V_t - V_{th}),$$3 from weak coupling $$n = (C_s/e)(V_s - V_s^d) + (\alpha C_t^0/e)(V_t - V_{th}),$$4 to strong coupling $$n = (C_s/e)(V_s - V_s^d) + (\alpha C_t^0/e)(V_t - V_{th}),$$5, permitting continuous evolution from two weakly coupled dots to a single “molecular” dot. At the same time, some nonmonotonicities in $$n = (C_s/e)(V_s - V_s^d) + (\alpha C_t^0/e)(V_t - V_{th}),$$6 are attributed to residual substrate or edge disorder, indicating that lithographic simplicity does not eliminate edge-induced electrostatic complexity.

3. Depletion-mode hole dots in intrinsic silicon

Amitonov et al. realize single-layer depletion-mode quantum dots in intrinsic silicon by first creating a two-dimensional hole gas and then locally depleting it with one metal gate layer (Amitonov et al., 2017). The material stack is intrinsic Si with resistivity $$n = (C_s/e)(V_s - V_s^d) + (\alpha C_t^0/e)(V_t - V_{th}),$$7, 7 nm thermal SiO$$n = (C_s/e)(V_s - V_s^d) + (\alpha C_t^0/e)(V_t - V_{th}),$$8, and 5 nm ALD Al$$n = (C_s/e)(V_s - V_s^d) + (\alpha C_t^0/e)(V_t - V_{th}),$$9O$\alpha \simeq 1/11.7$0 deposited using TMA/H$\alpha \simeq 1/11.7$1O at $\alpha \simeq 1/11.7$2. After annealing in Ar at 100 Pa and $\alpha \simeq 1/11.7$3 for 30 min, hydrogen diffuses from the Al$\alpha \simeq 1/11.7$4O$\alpha \simeq 1/11.7$5 toward the SiO$\alpha \simeq 1/11.7$6/Si interface and passivates dangling bonds, while non-stoichiometric Al$\alpha \simeq 1/11.7$7O$\alpha \simeq 1/11.7$8 near the interface captures electrons in deep traps. The resulting fixed negative charge is $\alpha \simeq 1/11.7$9–$E_M$0.

This immobile negative charge pulls holes to the Si/SiO$E_M$1 interface. Once $E_M$2 exceeds the surface-potential barrier, a conducting 2DHG forms without any applied gate voltage. Local depletion is then achieved with thermally evaporated Al gates patterned by electron-beam lithography and lift-off. After gate lift-off, a 5 nm ALD Al$E_M$3O$E_M$4 protection layer caps the gates during the final anneal. Two geometries are demonstrated. The “ABC” geometry uses five top/bottom finger-gate pairs with approximately 75–100 nm inter-finger gaps, and the “XYZ” geometry, adapted from Ciorga et al., uses three coplanar gates with approximately 75 nm pitch to define a single quantum dot. Typical lithographic dimensions are finger widths of 50–100 nm and spacings of 60–80 nm, yielding an island size of approximately 75 nm.

Electrical characterization confirms depletion-mode operation. In the “ABC” device, the two-terminal channel current $E_M$5 is completely turned off at $E_M$6 V. Transport spectroscopy of a few-hole dot between gates B/b and C/c gives a last visible Coulomb diamond with $E_M$7 meV and therefore $E_M$8 F. In the “XYZ” geometry, clear Coulomb oscillations yield $E_M$9–$<1$0 meV and $<1$1 F. Using $<1$2, the estimated island radius is $<1$3–35 nm, corresponding to a diameter of about 60–70 nm and matching lithography. The charging energy is extracted either from

$<1$4

or directly from the Coulomb-diamond height using

$<1$5

The architecture avoids complex multilayer gate stacks requiring precision alignment, but the paper also identifies the characteristic design constraints of single-layer depletion gates. Single-layer gates inevitably capacitively couple to neighboring regions, so narrow fingers, small overlaps, and optimized dielectric thicknesses are required to maintain independent control. The current e-beam resolution is reported as about 20–30 nm, and combined with overlay error it sets a minimal gate-to-gate pitch of about 30 nm. Non-uniform $<1$6 across the wafer can shift thresholds, and deep-UV/ozone exposure at 254 nm for 10–20 min can neutralize $<1$7, remove unintended 2DHG formation, and restore intrinsic-Si behavior.

4. Single-metal-layer electron dots in undoped Si/SiGe

Lu et al. extend the single-layer strategy to undoped Si/Si$<1$8Ge$<1$9 electron quantum dots using only one metal-gate layer (Lu et al., 2016). The heterostructure consists of a Si (001) substrate, a 2 $\sim4$0 linearly graded Si$\sim4$1Ge$\sim4$2 buffer with $\sim4$3 increasing from 0 to 0.2 at 10%/$\sim4$4, a 1 $\sim4$5 relaxed Si$\sim4$6Ge$\sim4$7 buffer polished by CMP with 150 nm removed, 400 nm Si$\sim4$8Ge$\sim4$9, a 20 nm strained Si quantum well, a 35 nm Si$\psi_s \approx (Q_f + Q_{it})/C_{ox},$00Ge$\psi_s \approx (Q_f + Q_{it})/C_{ox},$01 barrier, a 3 nm Si cap, a 15–20 nm Al$\psi_s \approx (Q_f + Q_{it})/C_{ox},$02O$\psi_s \approx (Q_f + Q_{it})/C_{ox},$03 dielectric, and a 100 nm Al gate or a Ti/Au stack of 2 nm/40 nm for dot devices.

A defining materials issue is the reduced conduction-band offset $\psi_s \approx (Q_f + Q_{it})/C_{ox},$04 relative to the more common 30% Ge barrier systems. The paper states that the 20% Ge barrier is approximately 100 meV shallower, which reduces the maximum 2DEG density to $\psi_s \approx (Q_f + Q_{it})/C_{ox},$05, compared with approximately $\psi_s \approx (Q_f + Q_{it})/C_{ox},$06 for 30% Ge. This narrows the operational gate-bias window. The lower bound is set by $\psi_s \approx (Q_f + Q_{it})/C_{ox},$07, where threshold rises as the channel narrows; the upper bound is $\psi_s \approx (Q_f + Q_{it})/C_{ox},$08, above which a parallel surface channel forms and the buried quantum-well channel pinches off, producing a sudden current drop. For Si$\psi_s \approx (Q_f + Q_{it})/C_{ox},$09Ge$\psi_s \approx (Q_f + Q_{it})/C_{ox},$10, $\psi_s \approx (Q_f + Q_{it})/C_{ox},$11 is reported as about 2 V, device-dependent.

The gate pattern is a single-layer finger-gate geometry. Wire-channel FETs with widths from 100 nm to 5 $\psi_s \approx (Q_f + Q_{it})/C_{ox},$12 are used for threshold studies, and the quantum-dot device uses seven finger gates per channel: LL, UL, UC, UR, LR, AGL, and AGU. The narrowest point of the gated channel is about 200 nm wide. UL and UR serve as plunger gates while also weakly affecting tunnel barriers, UC primarily tunes the interdot barrier, and AGL/AGU induce reservoir 2DEGs.

The experimentally important result is that threshold voltage rises strongly as width decreases. For $\psi_s \approx (Q_f + Q_{it})/C_{ox},$13 nm, the threshold shift $\psi_s \approx (Q_f + Q_{it})/C_{ox},$14 is of the order of hundreds of mV, and $\psi_s \approx (Q_f + Q_{it})/C_{ox},$15 nm wires often fail to turn on at gate voltages up to 2 V. Lu et al. fit this behavior with a confinement model

$\psi_s \approx (Q_f + Q_{it})/C_{ox},$16

with $\psi_s \approx (Q_f + Q_{it})/C_{ox},$17 and goodness of fit $\psi_s \approx (Q_f + Q_{it})/C_{ox},$18. The device can nevertheless be tuned from a single dot to a double dot. At modest $\psi_s \approx (Q_f + Q_{it})/C_{ox},$19, for example $\psi_s \approx (Q_f + Q_{it})/C_{ox},$20 V, two-dimensional plots versus $\psi_s \approx (Q_f + Q_{it})/C_{ox},$21 show parallel single-dot Coulomb oscillations with slope approximately 1:1. As $\psi_s \approx (Q_f + Q_{it})/C_{ox},$22 becomes more negative, approaching $\psi_s \approx (Q_f + Q_{it})/C_{ox},$23 V, the single dot splits into a double-dot honeycomb or triple-point pattern. In the double-dot regime, the reported example capacitances are $\psi_s \approx (Q_f + Q_{it})/C_{ox},$24 aF, $\psi_s \approx (Q_f + Q_{it})/C_{ox},$25 aF, and $\psi_s \approx (Q_f + Q_{it})/C_{ox},$26 aF, giving $\psi_s \approx (Q_f + Q_{it})/C_{ox},$27.

This system makes explicit a central limitation of single-layer depletion fine gates: the gain in fabrication simplicity comes with reduced orthogonality of control. The paper states that plunger gates also influence barriers, that single-metal-layer cross-coupling complicates tuning, and that the constrained bias window requires larger lithographic dots. Suggested improvements are higher Ge content, thinner high-$\psi_s \approx (Q_f + Q_{it})/C_{ox},$28 dielectrics such as HfO$\psi_s \approx (Q_f + Q_{it})/C_{ox},$29, and hybrid schemes combining a global reservoir gate with single-layer fine gates.

5. III–V depletion architectures: direct top-gate depletion and screened local writing

In InSb quantum wells, Uddin et al. study a single Al$\psi_s \approx (Q_f + Q_{it})/C_{ox},$30O$\psi_s \approx (Q_f + Q_{it})/C_{ox},$31-insulated top gate designed to fully deplete a 2DEG (Uddin et al., 2013). In the structure with the Al$\psi_s \approx (Q_f + Q_{it})/C_{ox},$32In$\psi_s \approx (Q_f + Q_{it})/C_{ox},$33Sb surface layer, the stack is metal gate / 40 nm ALD Al$\psi_s \approx (Q_f + Q_{it})/C_{ox},$34O$\psi_s \approx (Q_f + Q_{it})/C_{ox},$35 / 30 nm Al$\psi_s \approx (Q_f + Q_{it})/C_{ox},$36In$\psi_s \approx (Q_f + Q_{it})/C_{ox},$37Sb surface layer / 20 nm Al$\psi_s \approx (Q_f + Q_{it})/C_{ox},$38In$\psi_s \approx (Q_f + Q_{it})/C_{ox},$39Sb barrier / $\psi_s \approx (Q_f + Q_{it})/C_{ox},$40 nm InSb quantum well. At zero bias, the Schottky-barrier height is $\psi_s \approx (Q_f + Q_{it})/C_{ox},$41 eV and the 2DEG density is $\psi_s \approx (Q_f + Q_{it})/C_{ox},$42. Under negative gate bias, the well conduction band rises relative to $\psi_s \approx (Q_f + Q_{it})/C_{ox},$43, and full pinch-off occurs at $\psi_s \approx (Q_f + Q_{it})/C_{ox},$44 V. Experimentally, $\psi_s \approx (Q_f + Q_{it})/C_{ox},$45 decreases linearly with $\psi_s \approx (Q_f + Q_{it})/C_{ox},$46 from 0 to $\psi_s \approx (Q_f + Q_{it})/C_{ox},$47 V, with $\psi_s \approx (Q_f + Q_{it})/C_{ox},$48, and the hysteresis is below 50 mV over multiple sweeps. By contrast, an otherwise identical structure with an InSb surface cap shows a nonlinear and shallow density response, strong hysteresis of about 0.5–1 V, and slow response due to hole screening and charge trapping in Al$\psi_s \approx (Q_f + Q_{it})/C_{ox},$49O$\psi_s \approx (Q_f + Q_{it})/C_{ox},$50. The wider-bandgap Al$\psi_s \approx (Q_f + Q_{it})/C_{ox},$51In$\psi_s \approx (Q_f + Q_{it})/C_{ox},$52Sb surface layer keeps the surface valence band well below $\psi_s \approx (Q_f + Q_{it})/C_{ox},$53, suppressing hole accumulation and enabling linear, sharp depletion.

Bachsoliani et al. implement a conceptually different single-layer depletion architecture in GaAs/AlGaAs by globally depleting the 2DES with a top gate and locally screening that field with nanoscale screen gates patterned directly on the wafer surface (Bachsoliani et al., 2017). The heterostructure includes a 5 nm GaAs cap, 70 nm Si-doped Al$\psi_s \approx (Q_f + Q_{it})/C_{ox},$54Ga$\psi_s \approx (Q_f + Q_{it})/C_{ox},$55As, 35 nm undoped Al$\psi_s \approx (Q_f + Q_{it})/C_{ox},$56Ga$\psi_s \approx (Q_f + Q_{it})/C_{ox},$57As spacer, and the GaAs quantum well. The gate stack places Ti/Au screen gates directly on the cap, then a 100 nm cross-linked PMMA dielectric, and finally a Ti/Au global top gate covering the mesa. The 2DES–screen-gate spacing is 110 nm, and the screen-gate–top-gate spacing is 100 nm. Typical screen-gate wire widths are 200–300 nm.

The electrostatics are described by a screened-capacitor model. The top gate alone fully depletes the bare 2DES at $\psi_s \approx (Q_f + Q_{it})/C_{ox},$58 V. Under a screen-gate finger, the effective top-gate coupling is reduced by $\psi_s \approx (Q_f + Q_{it})/C_{ox},$59, and the local density is

$\psi_s \approx (Q_f + Q_{it})/C_{ox},$60

with screen-gate depletion voltage $\psi_s \approx (Q_f + Q_{it})/C_{ox},$61 V. Hall-bar measurements at 4.2 K show $\psi_s \approx (Q_f + Q_{it})/C_{ox},$62 rising linearly from zero at $\psi_s \approx (Q_f + Q_{it})/C_{ox},$63 V to $\psi_s \approx (Q_f + Q_{it})/C_{ox},$64 at $\psi_s \approx (Q_f + Q_{it})/C_{ox},$65, while mobility increases to $\psi_s \approx (Q_f + Q_{it})/C_{ox},$66 near $\psi_s \approx (Q_f + Q_{it})/C_{ox},$67 V. The reported lateral resolution is characterized by a capacitance ratio $\psi_s \approx (Q_f + Q_{it})/C_{ox},$68 near pinch-off and numerical Poisson solutions showing sub-100 nm depletion tails. In an Aharonov–Bohm ring of area $\psi_s \approx (Q_f + Q_{it})/C_{ox},$69, the AB period is $\psi_s \approx (Q_f + Q_{it})/C_{ox},$70 mT and the visibility is about 2–5% at $\psi_s \approx (Q_f + Q_{it})/C_{ox},$71 mV and $\psi_s \approx (Q_f + Q_{it})/C_{ox},$72 mV; Coulomb-blockade oscillations in $\psi_s \approx (Q_f + Q_{it})/C_{ox},$73 indicate accidental quantum dots in each arm.

Taken together, the InSb and GaAs cases show two different depletion logics. In InSb, a single insulated top gate linearly removes a pre-existing 2DEG. In GaAs, a global depletion gate removes the 2DES everywhere except where a local single-layer screen gate preserves it. The latter is especially important for complex topologies: the paper explicitly notes that a $\psi_s \approx (Q_f + Q_{it})/C_{ox},$74 dot chain could be implemented with $\psi_s \approx (Q_f + Q_{it})/C_{ox},$75 screen gates instead of approximately $\psi_s \approx (Q_f + Q_{it})/C_{ox},$76 traditional gates.

6. Built-in depletion-charge gates and recurrent design constraints

Xu and Luo push the depletion concept beyond lithographically biased electrodes by using a thin, heavily p-doped Si region as a built-in fine gate in an all-Si GAAFET-like structure (Xu et al., 23 Jan 2025). Their simulated device uses a lightly p-doped Si channel with $\psi_s \approx (Q_f + Q_{it})/C_{ox},$77, top and bottom HfO$\psi_s \approx (Q_f + Q_{it})/C_{ox},$78 of thickness 1 nm and $\psi_s \approx (Q_f + Q_{it})/C_{ox},$79, metal gates of work function $\psi_s \approx (Q_f + Q_{it})/C_{ox},$80 eV, thickness 4 nm and length 5 nm, and gate-to-gate spacing of 5 nm. In the spacer or underlap region beyond each gate, a 4 nm-thick, heavily p-doped Si slab is inserted and connected to the $\psi_s \approx (Q_f + Q_{it})/C_{ox},$81 source and drain with $\psi_s \approx (Q_f + Q_{it})/C_{ox},$82. The nominal p-region parameters are $\psi_s \approx (Q_f + Q_{it})/C_{ox},$83, length $\psi_s \approx (Q_f + Q_{it})/C_{ox},$84 nm, and thickness $\psi_s \approx (Q_f + Q_{it})/C_{ox},$85 nm.

The electrostatics are solved by finite-difference Poisson and Schrödinger equations. In each grid cell,

$\psi_s \approx (Q_f + Q_{it})/C_{ox},$86

with $\psi_s \approx (Q_f + Q_{it})/C_{ox},$87, $\psi_s \approx (Q_f + Q_{it})/C_{ox},$88 on the gates, $\psi_s \approx (Q_f + Q_{it})/C_{ox},$89 in the $\psi_s \approx (Q_f + Q_{it})/C_{ox},$90 source/drain, and $\psi_s \approx (Q_f + Q_{it})/C_{ox},$91 at far-field boundaries. The built-in depletion width in the p-region is

$\psi_s \approx (Q_f + Q_{it})/C_{ox},$92

For $\psi_s \approx (Q_f + Q_{it})/C_{ox},$93 and $\psi_s \approx (Q_f + Q_{it})/C_{ox},$94 at 300 K, $\psi_s \approx (Q_f + Q_{it})/C_{ox},$95 eV and $\psi_s \approx (Q_f + Q_{it})/C_{ox},$96–6 nm. When $\psi_s \approx (Q_f + Q_{it})/C_{ox},$97, the p-slab is fully depleted and supports a uniform negative space charge $\psi_s \approx (Q_f + Q_{it})/C_{ox},$98. Along the channel centerline,

$\psi_s \approx (Q_f + Q_{it})/C_{ox},$99

and a one-dimensional estimate gives a barrier hump

$V_{th}\simeq -Q_f/C_{ox}.$00

The simulations report four pronounced peaks in the 2D conduction-band map at the p-regions. Along the center line, $V_{th}\simeq -Q_f/C_{ox}.$01 nm and $V_{th}\simeq -Q_f/C_{ox}.$02 at $V_{th}\simeq -Q_f/C_{ox}.$03 V produce two barriers each about 550 meV above $V_{th}\simeq -Q_f/C_{ox}.$04. Reducing $V_{th}\simeq -Q_f/C_{ox}.$05 to 8 nm and increasing $V_{th}\simeq -Q_f/C_{ox}.$06 to $V_{th}\simeq -Q_f/C_{ox}.$07 produces slightly lower barriers of about 530 meV with smaller width. For $V_{th}\simeq -Q_f/C_{ox}.$08 nm and $V_{th}\simeq -Q_f/C_{ox}.$09, the barrier changes from about 300 meV at $V_{th}\simeq -Q_f/C_{ox}.$10 V to about 60 meV at $V_{th}\simeq -Q_f/C_{ox}.$11 V. The extracted barrier-height shift can be mapped to an effective $V_{th}\simeq -Q_f/C_{ox}.$12–0.4 V, and the authors state that a subthreshold slope below 60 mV/dec is in principle possible, while noting that exact values require transport simulations with finite $V_{th}\simeq -Q_f/C_{ox}.$13.

This suggests that the notion of a fine gate can be generalized from a patterned electrode to any sufficiently localized depletion source. The surveyed literature also clarifies several recurring misconceptions. First, single-layer architectures do not eliminate electrostatic cross-coupling: intrinsic-Si devices note that single-layer gates inevitably capacitively couple to neighboring regions, and the Si/SiGe dot device reports that $V_{th}\simeq -Q_f/C_{ox}.$14 and $V_{th}\simeq -Q_f/C_{ox}.$15 also weakly modulate barrier height (Amitonov et al., 2017, Lu et al., 2016). Second, a fine gate need not be a metal feature: the graphene device uses narrow graphene fingers within the active sheet, and the all-Si GAAFET study uses a fully depleted p-doped strip as a built-in floating gate (Wang et al., 2011, Xu et al., 23 Jan 2025). Third, fabrication simplification does not suppress materials problems. The relevant constraints recur with different physical origins: residual substrate or edge disorder in graphene, non-uniform fixed charge in SiO$V_{th}\simeq -Q_f/C_{ox}.$16/Al$V_{th}\simeq -Q_f/C_{ox}.$17O$V_{th}\simeq -Q_f/C_{ox}.$18, interface traps in InSb, and possible mobility degradation from ultra-high near-channel doping in the all-Si depletion-charge approach (Wang et al., 2011, Amitonov et al., 2017, Uddin et al., 2013, Xu et al., 23 Jan 2025).

The overall record therefore presents single-layer depletion fine gates not as a single device recipe but as an electrostatic design class. Its common advantages are reduced lithographic complexity, fewer aligned gate levels, and direct access to sub-100 nm or even few-nanometer control regions. Its common limitations are restricted bias windows, reduced orthogonality between plungers and barriers, threshold sensitivity to confinement and disorder, and the need for precise dielectric and interface engineering.