Distributed Sparse Ising Machine (DSIM)

• DSIM is a scalable probabilistic computing platform that networks FPGAs to sample from and optimize large-scale Ising models.
• It utilizes local on-chip memory for couplings and biases with 1-bit exchanges per boundary spin, reducing inter-device traffic.
• The system achieves multi-trillion flip-per-second rates and establishes design rules that balance throughput and sampling accuracy.

The Distributed Sparse Ising Machine (DSIM) is a scalable probabilistic computing platform implemented by networking multiple Field-Programmable Gate Arrays (FPGAs) to sample from and optimize Ising models significantly exceeding single-chip resource and memory constraints. Leveraging programmable “p-bits,” each node in the DSIM collectively builds a distributed architecture that performs Gibbs sampling at multi-trillion flip-per-second rates, maintaining all coupling weights and biases in local on-chip memory and minimizing inter-device communication to 1-bit exchange per boundary spin. The DSIM provides a programmable and empirical platform for advancing stochastic optimization and sampling, with demonstrated applications in spin glass physics, Max-Cut, and Boolean satisfiability, and establishes quantitative design rules for partitioned machine accuracy and throughput (Aadit et al., 24 Jun 2026).

1. System Architecture and Block-Level Organization

Each DSIM node consists of an FPGA implementing a “partition” of a global sparse Ising graph. Within each FPGA:

• Local on-chip memories store all intra-partition couplings $J_{ij}$ and p-bit biases $\theta_i$; no weights traverse the interconnect.
• Banks of programmable p-bits ($N_{\rm p-bit}$), e.g., $\approx50,000$ p-bits/FPGA for $37^3$ lattices or $\approx13,900$ p-bits/Super Logic Region for $100^3$ lattices.
• P-bits within each partition are divided into $N_{\rm color}$ independent color groups via graph coloring to facilitate parallel update of all p-bits in a given group.
• Multiple FPGAs are interconnected in a sparse, boundary-only communication topology (e.g., 6-device chains in DSIM-1 or 18-board rectangles in DSIM-2). Within each FPGA, further sub-partitioning (along Super Logic Region boundaries) with “shadow-weight” duplication addresses extremely large graphs.

The partitioning scheme ensures that all memory-intensive aspects of the Ising graph are handled locally; inter-FPGA traffic only consists of minimal p-bit boundary information for edges linking partitions.

2. Gibbs Sampling and P-bit Update Rule

Each p-bit $i$ maintains a state $s_i \in \{+1, -1\}$. Updates utilize Gibbs sampling:

$\theta_i$0

with the local field

$\theta_i$1

where $\theta_i$2 is the inverse temperature and $\theta_i$3. Alternatively, one may sample via

$\theta_i$4

with $\theta_i$5. The probabilistic logic is mapped directly onto hardware, with color-group parallelism determining which p-bits can be flipped simultaneously without update conflicts.

3. Partitioned Communication and the Timing Ratio $\theta_i$6

After graph partitioning, each cross-partition edge duplicates its $\theta_i$7 (“shadowed”) onto both participant FPGAs. At runtime, only the state $\theta_i$8 and $\theta_i$9 for boundary p-bits must be exchanged, comprising 1 bit per direction per edge. The p-bits in non-boundary regions remain strictly local.

Two key clock domains govern DSIM performance:

• $N_{\rm p-bit}$0: the local p-bit update rate (spin flips per second, per p-bit)
• $N_{\rm p-bit}$1: boundary-bit transfer rate

The single dimensionless parameter

$N_{\rm p-bit}$2

regulates the staleness of boundary p-bit data and, consequently, the system’s effective fidelity to the unpartitioned (monolithic) Ising sampler.

A conservative design rule prohibits local updates from overtaking boundary refreshes:

$N_{\rm p-bit}$3

where $N_{\rm p-bit}$4 is the number of color groups and $N_{\rm p-bit}$5 is the maximum congestion (worst-case boundary-traffic factor). System performance saturates to the monolithic case when

$N_{\rm p-bit}$6

For example, in a $N_{\rm p-bit}$7 system with $N_{\rm p-bit}$8 and $N_{\rm p-bit}$9, the threshold is $\approx50,000$0.

4. Universality of Partitioning Tradeoff: Cluster Mean-Field Theory

The system’s critical throughput-accuracy tradeoff is captured by parallel cluster mean-field theory (CMFT), mapping each FPGA partition to a “cluster.” Within a cluster, full Gibbs sampling is executed locally, but boundary spins of adjacent clusters are held fixed at their mean field averages for $\approx50,000$1 sweeps, then updated.

Given $\approx50,000$2 (state of boundary spin $\approx50,000$3 at sweep $\approx50,000$4):

$\approx50,000$5

Cluster $\approx50,000$6 then computes fields using these mean boundaries until the next exchange.

Here, $\approx50,000$7 (exchange interval) is the analog of $\approx50,000$8 in hardware: $\approx50,000$9 ($37^3$0) gives monolithic equivalence; large $37^3$1 (small $37^3$2) induces greater staleness. Empirically and in simulation:

• Frequent exchange ($37^3$3 or $37^3$4): residual energy decays with exponent $37^3$5 matching ground truth (e.g., $37^3$6).
• Infrequent exchange ($37^3$7, $37^3$8): the decay exhibits a smoothly reduced exponent $37^3$9.

A one-parameter rescaling collapses hardware and mean-field results onto a universal curve, demonstrating the intrinsic nature of this partition-induced tradeoff in stochastic dynamics.

5. Quantitative Performance Metrics and Throughput-Accuracy Curves

The DSIM’s computational throughput is expressed as:

$\approx13,900$0

with $\approx13,900$1 the global p-bit count. Empirical results for two configurations:

System	FPGAs	$\approx13,900$2	$\approx13,900$3	Flips/sec	$\approx13,900$4 (slope)
DSIM-1	6	$\approx13,900$5	$\approx13,900$6 MHz	$\approx13,900$7	$\approx13,900$8 (GPU: $\approx13,900$9)
			$100^3$0 MHz (overclocked)	$100^3$1	$100^3$2
DSIM-2	18	$100^3$3	$100^3$4 MHz	$100^3$5	$100^3$6 (GPU: $100^3$7)
			$100^3$8 MHz (overclocked)	$100^3$9	$N_{\rm color}$0

Time-to-target analysis shows “easy” targets (higher residual energy $N_{\rm color}$1) benefit from overclocking (up to hundreds-fold speedup), while for ultra-low $N_{\rm color}$2 the accuracy cost (reduced $N_{\rm color}$3) outweighs throughput, with the crossover dictated by slopes and flip-rate ratio.

6. Empirical Demonstrations and Applications

DSIM has demonstrated performance across diverse problems:

• 3D Edwards–Anderson Spin Glasses: DSIM and monolithic GPU reference systems yield identical power-law exponents ($N_{\rm color}$4 for $N_{\rm color}$5, $N_{\rm color}$6 for $N_{\rm color}$7). Overclocked DSIMs manifest the predicted $N_{\rm color}$8-controlled exponent reduction.
• Max-Cut (Gset G81, 20,000 nodes): Augmented with adaptive parallel tempering and isoenergetic cluster moves, DSIM-1 at $N_{\rm color}$9 achieves the certified-optimal cut (14,060), with a 14% hit rate, matching leading heuristic and exact solvers.
• Boolean Satisfiability (3SAT, near phase transition): For $i$0 variables and $i$1 clauses (mapped to $i$2 p-bits with invertible logic/copy gates), DSIM-2 at $i$3 matches GPU progress up to $i$4 sweeps, reaching $i$5 clause satisfaction.

The architecture’s ability to preserve solution quality hinges on maintaining $i$6 above the partition-dependent threshold. If $i$7 drops below this threshold, the residual energy decay exponent decreases, introducing a quantifiable and predictable throughput-accuracy tradeoff managed at system configuration time.

7. Scaling Implications and Design Rules

DSIM demonstrates that scaling probabilistic computers for Ising models beyond single-chip limitations is feasible when all couplings remain strictly local and only minimal state information is exchanged across partitions. The dimensionless timing ratio $i$8 provides a tunable handle for system designers: above the threshold $i$9, partitioning is transparent and the system is mathematically indistinguishable from its monolithic counterpart; below, solution quality degrades in a quantitatively predictable manner. Cluster mean-field theory verifies the universality of this throughput-accuracy tradeoff, supplying a quantitative design framework for partitioned stochastic systems at scale (Aadit et al., 24 Jun 2026).