FeFET-based QUBO Solvers for Combinatorial Optimization

• The paper presents a novel FeFET-based architecture that maps QUBO problems directly onto crossbar arrays, reducing the need for auxiliary variables and shrinking the search space significantly.
• FeFET devices, with their multilevel programmability, high endurance, and non-volatility, are integrated into CiM and oscillator-based platforms to achieve marked improvements in energy efficiency, area savings, and computational speed.
• Experimental results highlight that architectures like HyCiM and FeFET-coupled oscillator Ising machines deliver up to 98.54% solution quality with 88–99.96% area savings compared to conventional D-QUBO methods.

FeFET-based QUBO solvers are specialized hardware accelerators leveraging ferroelectric field-effect transistors (FeFETs) within compute-in-memory (CiM) or oscillator-based architectures to solve quadratic unconstrained binary optimization (QUBO) problems. These solvers exploit the non-volatility, analog programmability, and high endurance of FeFET devices for both encoding problem coefficients and in-memory computation, providing an energy-efficient, fast, and scalable alternative for tackling combinatorial optimization problems (COPs) with or without constraints. Several architectures, including the HyCiM system and FeFET-coupled oscillator Ising machines, have demonstrated substantial improvements in search-space reduction, area efficiency, and computation speed, with practical performance validated on non-trivial problem instances such as quadratic knapsack, graph coloring, Max-Cut, and MIMO detection (Qian et al., 2024, Yin et al., 2023, Jadia et al., 1 Nov 2025).

1. QUBO Formulation and Mapping to FeFET Hardware

QUBO problems are expressed as

$E(\mathbf{x}) = \mathbf{x}^T Q\,\mathbf{x}$

with binary variables $\mathbf{x} \in \{0,1\}^n$ and coefficient matrix $Q \in \mathbb{R}^{n \times n}$. The binary optimization can encode COPs, including those represented by Ising Hamiltonians via the mapping $\sigma_i = 1-2x_i$:

$$H_P(\boldsymbol{\sigma}) = \sum_{i<j} J_{ij} \sigma_i \sigma_j + \sum_i h_i \sigma_i$$

with $E(\mathbf{x}) = \mathbf{x}^T Q \mathbf{x}$ after transformation (Yin et al., 2023, Qian et al., 2024).

FeFET-based solvers map this QUBO directly onto crossbar arrays, exploiting the programmable multilevel $V_{\text{th}}$ of FeFETs to represent matrix coefficients with digital or analog precision. For problems with constraints—especially inequality constraints (e.g., knapsack-type)—conventional D-QUBO approaches penalize violations within the objective, necessitating large numbers of auxiliary variables and significantly expanding the state space ($2^{n+C}$ for $n$ variables and constraint $C$). FeFET architectures such as HyCiM instead separate feasibility checking and energy evaluation, allowing direct mapping of feasible configurations only (Qian et al., 2024).

2. FeFET Device Architecture and Crossbar Implementation

FeFETs are three-terminal, CMOS-compatible transistors with a ferroelectric HfO₂ gate dielectric, providing high ON/OFF ratios (>10³), multilevel storage via polarization programming, endurance (>10¹⁰ cycles), and ≥10-year data retention. In a 28 nm process, FeFETs can be structured as 1FeFET–1R cells to further suppress read variation (Yin et al., 2023, Jadia et al., 1 Nov 2025).

Crossbar arrays organize FeFET cells to implement parallel vector-matrix-vector (VMV) multiplication ($\mathbf{x} \in \{0,1\}^n$0) in a single computational step:

• Data Encoding: Input variables $\mathbf{x} \in \{0,1\}^n$1 are supplied on wordlines (WL), and coefficients $\mathbf{x} \in \{0,1\}^n$2 are represented by programmable $\mathbf{x} \in \{0,1\}^n$3 in FeFETs or by conductance in crossbar patterns.
• Parallel Computation: For each SA iteration, candidate $\mathbf{x} \in \{0,1\}^n$4 is broadcast, row and column currents representing energy are summed and digitized; at M-bit precision, multiple bit-sliced crossbars or per-cell quantization can be employed.
• Scalability: Arrays are implemented at 32×32 size in silicon with tiling to support $\mathbf{x} \in \{0,1\}^n$5 variables; lossless matrix compression further improves density (Yin et al., 2023).

3. FeFET-based Solvers for Constrained QUBO: The Inequality-Filter Paradigm

Traditional D-QUBO methods for combinatorial problems with constraints require embedding

$\mathbf{x} \in \{0,1\}^n$6

as a penalty, leading to an augmented space ($\mathbf{x} \in \{0,1\}^n$7). The HyCiM architecture introduces a novel transformation that enforces constraints via a dedicated inequality-checking circuit (the "inequality filter") prior to QUBO energy evaluation (Qian et al., 2024):

• Device-circuit co-design: Each inequality-filter cell is a 1FeFET–1R stack, storing multi-level weights and supporting current-mode, phase-based comparison of partial sums.
• Array operation: An $\mathbf{x} \in \{0,1\}^n$8 array stores weights across $\mathbf{x} \in \{0,1\}^n$9 columns, with match-line voltages encoding $Q \in \mathbb{R}^{n \times n}$0. A replica array encodes the constraint $Q \in \mathbb{R}^{n \times n}$1; a two-stage comparator passes only feasible $Q \in \mathbb{R}^{n \times n}$2 for VMV evaluation.
• Impact: This approach removes the need for auxiliary bits, reducing the search space from up to $Q \in \mathbb{R}^{n \times n}$3 ($Q \in \mathbb{R}^{n \times n}$4, $Q \in \mathbb{R}^{n \times n}$5) to only $Q \in \mathbb{R}^{n \times n}$6, and delivering hardware area savings of 88–99.96%.

4. Annealing Algorithms, Compression, and Computational Workflow

FeFET-based QUBO solvers commonly employ simulated annealing (SA) or enhanced variants such as MESA (multi-epoch SA):

• Annealing Process: At each iteration, candidate configurations $Q \in \mathbb{R}^{n \times n}$7 are tested against feasibility constraints (if present), and energies $Q \in \mathbb{R}^{n \times n}$8 are computed in-place in the crossbar. Acceptance follows the Metropolis rule:

$Q \in \mathbb{R}^{n \times n}$9

with exponential or linear temperature decay (Qian et al., 2024).

• Sparse QUBO Compression: For sparse problems, compression maps the Q matrix to reduced-dimension blocks without energy loss; for example, producing dimension $\sigma_i = 1-2x_i$0 with $\sigma_i = 1-2x_i$1, reducing area by 60–80% (Yin et al., 2023).
• Oscillator Ising Machines: Alternative architectures map QUBO couplings onto FeFET-controlled conductances in coupled oscillator arrays ("OIMs"). Oscillator phase synchronization, modeled by discrete Kuramoto dynamics, enables all-to-all QUBO minimization with time-to-solution scaling as $\sigma_i = 1-2x_i$2 (Jadia et al., 1 Nov 2025).

5. Performance Metrics and Experimental Results

FeFET-based QUBO solvers exhibit significant improvements in benchmarked metrics:

Metric	HyCiM (FeFET CiM)	D-QUBO Baseline	OIM (FeFET+CMOS)
Search Space	$\sigma_i = 1-2x_i$3 (w/ filter)	up to $\sigma_i = 1-2x_i$4	$\sigma_i = 1-2x_i$5 (M spins)
Area Savings	88–99.96% vs. D-QUBO	—	N/A
SA Time-to-solution	$\sigma_i = 1-2x_i$6–$\sigma_i = 1-2x_i$7s @ $\sigma_i = 1-2x_i$8	$\sigma_i = 1-2x_i$9 higher	$$H_P(\boldsymbol{\sigma}) = \sum_{i<j} J_{ij} \sigma_i \sigma_j + \sum_i h_i \sigma_i$$0 scaling
Solution Quality	98.54% success (QKP)	10.75% (QKP)	Near-ML BER, $$H_P(\boldsymbol{\sigma}) = \sum_{i<j} J_{ij} \sigma_i \sigma_j + \sum_i h_i \sigma_i$$1

Additional results include:

• Energy per QUBO evaluation: $$H_P(\boldsymbol{\sigma}) = \sum_{i<j} J_{ij} \sigma_i \sigma_j + \sum_i h_i \sigma_i$$22 pJ (crossbar), 0.5 pJ (filter) (Qian et al., 2024).
• MESA achieves target energies in 10–100× fewer iterations than conventional SA (Yin et al., 2023).
• Ring-Oscillator FeFET OIMs achieve logarithmic computation time scaling for dense QUBOs such as MIMO detection, limited by conductance tuning windows (1–60 μS per device) (Jadia et al., 1 Nov 2025).

6. Device- and System-Level Considerations

FeFET-based designs are subject to various device-level effects and practical system constraints:

• Threshold Variation: Device-to-device $$H_P(\boldsymbol{\sigma}) = \sum_{i<j} J_{ij} \sigma_i \sigma_j + \sum_i h_i \sigma_i$$3 variation $$H_P(\boldsymbol{\sigma}) = \sum_{i<j} J_{ij} \sigma_i \sigma_j + \sum_i h_i \sigma_i$$4 mV; can be mitigated via calibration (Qian et al., 2024).
• Conductance Tuning: OIM performance is optimal for $$H_P(\boldsymbol{\sigma}) = \sum_{i<j} J_{ij} \sigma_i \sigma_j + \sum_i h_i \sigma_i$$5S, $$H_P(\boldsymbol{\sigma}) = \sum_{i<j} J_{ij} \sigma_i \sigma_j + \sum_i h_i \sigma_i$$6S; outside this window, coupling weakens or stalls.
• Endurance and Retention: HfO₂ FeFETs documented to $$H_P(\boldsymbol{\sigma}) = \sum_{i<j} J_{ij} \sigma_i \sigma_j + \sum_i h_i \sigma_i$$7 write/erase cycles and $$H_P(\boldsymbol{\sigma}) = \sum_{i<j} J_{ij} \sigma_i \sigma_j + \sum_i h_i \sigma_i$$8 years retention (Qian et al., 2024).
• Scalability: Demonstrated filter/annealer arrays range from 16×100 up to 256×256; crossbar chaining and compression allow scaling to $$H_P(\boldsymbol{\sigma}) = \sum_{i<j} J_{ij} \sigma_i \sigma_j + \sum_i h_i \sigma_i$$9–$E(\mathbf{x}) = \mathbf{x}^T Q \mathbf{x}$0 (Yin et al., 2023).
• Noise and Robustness: Simulated annealing and Kuramoto OIMs robust against analog noise; periodic refreshing mitigates drift.

7. Outlook and Application Domains

FeFET-based QUBO solvers offer a scalable platform for hardware acceleration of binary combinatorial optimizations:

• Versatility: Efficient support for both constraint-free and constrained COPs (e.g., quadratic knapsack, Max-Cut, graph coloring, ML MIMO detection).
• Integration: Three-terminal FeFETs compatible with advanced CMOS, enabling in-memory or near-memory compute paradigms.
• Future Prospects: Anticipated advances include denser 3D FeFET×CMOS integration, automated annealing protocols, expanded conductance range, and improved device uniformity. Applications extend to edge-AI, logistics, communication systems, and real-time optimization (Jadia et al., 1 Nov 2025, Qian et al., 2024, Yin et al., 2023).

FeFET-based QUBO solvers thus represent a leading architecture in the evolution of hardware-accelerated combinatorial optimization, providing order-of-magnitude benefits in energy, area, and solution speed, while maintaining competitive or superior solution quality on established benchmarks.