Compiled Wigner’s-Friend Circuits

• Compiled Wigner’s-friend-style circuits are explicitly engineered quantum circuits that model observer-dependent dynamics and enable measurement of inter-branch quantum correlators.
• They employ a unified gate model with controlled operations and optimized transpilation pipelines to simulate branching and validate theoretical predictions via experimental benchmarks.
• Measurement observables such as visibility and coherence witnesses provide quantifiable metrics for assessing device performance and probing quantum measurement collapse.

Compiled Wigner’s-friend-style circuits are explicit quantum circuits designed and implemented on programmable quantum hardware to probe operational “inter-branch” phenomena inspired by the Wigner’s friend thought experiment. These circuits encode branch-dependent, observer-involved dynamics within a unified gate model, enabling the measurement of correlators and witness observables that quantify coherence, branching, and measurement collapse in multi-register quantum systems. Modern implementations leverage circuit compilation pipelines targeting superconducting platforms, integrating simulation, transpilation, noise modeling, and statistical benchmarking for validation and reproducibility (Ding et al., 2021, Altman, 22 Jan 2026).

1. Conceptual Framework and Motivation

The Wigner’s friend scenario exposes the tension between unitary quantum evolution and measurement-induced collapse. Compiled circuit realizations map this scenario to explicit quantum registers: “friends” are internal qubit subsystems whose state is measured by external observers (“Wigners”) via controlled gate operations and measurement projectors. This circuit approach operationalizes Brukner’s no-go theorem for observer-independent facts and enables benchmarking of “inter-branch communication” through classical and quantum correlators directly extractable from measurement records (Ding et al., 2021, Altman, 22 Jan 2026).

Two primary motivations guide this compilation:

• Experimental accessibility: All relevant branches, recording devices, and outside observers are encapsulated within quantum hardware, making the scenario accessible to direct measurement and noise calibration.
• Operational benchmarking: The circuits act as testbeds for device coherence, gate infidelities, and the detection of any nonunitary channels or context transfer between quantum branches.

2. Circuit Architecture and Logical Partitioning

Compiled implementations map abstract Wigner’s-friend scenarios to multi-qubit circuits, with distinct registers assigned to “friends,” system signals, reference qubits, probe readouts, and auxiliary (ancilla) qubits. A canonical architecture is as follows:

Register	Role	Example Circuit (Ding et al., 2021, Altman, 22 Jan 2026)
Signal (a,b,c)	Main system qubits of each “lab”	3-qubit W state, tripartite scenario
Ancilla	Friends and recorders inside laboratories	Bell pairs, postselection, fusion register
Control (Q)	Wigner’s control qubit	Branch superposition, circuit-wide
Reference (R)	Message transfer/reference	Probes conditional correlation
Probe (P)	Readout probe register	Used for context-sensitive measurement
Auxiliary (A)	Controlled-swap ancilla	Enables Fredkin/Toffoli decomposition

For the tripartite example (Ding et al., 2021), nine physical qubits are partitioned into three signal qubits and three Bell ancilla pairs. In minimal “inter-branch witness” implementations, five logical qubits suffice, distributed to Q, R, F, P, and A (Altman, 22 Jan 2026).

3. Compilation, Gate Decomposition, and Transpilation Pipeline

The pipeline for compiled Wigner’s-friend-style circuits spans high-level gate specification to hardware execution:

• High-level design: Circuits are specified via quantum software (Q#, Qiskit), employing primitives $$\{H, X, R_y(\theta), U, \mathrm{CNOT}, \mathrm{CCX}, \text{Measure}\}$$.
• Ancilla initialization: Bell states are prepared using sequences of $H$ and CNOT, while W or @@@@3@@@@ use combinations of CNOTs and parametrized single-qubit rotations. For tripartite W state preparation:
  • 3 $X$ gates, 3 $R_y$ rotations, 4 CNOT gates (depth ≈ 8).
• Friend recording/fusion: CNOT-operated “fusion” between signal and ancilla with postselection implements partial measurement collapse analogues. Measurement postselection on $\alpha' = 0$ restricts to measurement-consistent branches.
• Branch divergence logic: In five-qubit “branch transfer” circuits, a controlled-unitary (e.g., controlled-Hadamard) conditions the “friend” evolution on the control (Wigner’s) qubit, while a controlled-swap (Fredkin) exchanges register states as a proxy for inter-branch “message transfer” (Altman, 22 Jan 2026).
• Compilation/transpilation: The designed circuits are lowered to OpenQASM and basis gates ($u3$, CNOT for IBM hardware), with further optimization for depth and gate count (optimization level 2 or 3 in Qiskit). Layout choices respect device coupling maps, with typical device assignment as $(Q,R,F,P,A) \to (q_2, q_3, q_5, q_6, q_7)$ on “heavy-hex” IBM topologies.

Typical gate counts and circuit depth for the tripartite scenario pre-optimization: $\sim$13 single-qubit gates, $\sim$10 two-qubit gates, depth $\sim$15, with further reduction by 10–20% in CX count and $\sim$15% in depth post-transpilation (Ding et al., 2021).

4. Measurement Observables and Witness Construction

Operational metrics for Wigner’s-friend-style circuits are formalized as classically accessible correlators or “witnesses”:

• Population-based visibility ($V$): Sensitive to diagonal elements, defined as

$V = |P(R=0\,|\,P=1) - P(R=1\,|\,P=1)|$

It is measured via shot statistics conditional on probe outcomes.

• Coherence witnesses ($W_X$, $W_Y$): Probe off-diagonal quantum coherence via many-body Pauli parity correlators,

$$W_X = \langle X_Q X_R X_F X_P \rangle, \quad W_Y = \langle Y_Q Y_R Y_F Y_P \rangle$$

Obtained by basis-rotated (e.g., Hadamard or $S^\dagger H$) measurement and parity analysis across all four relevant qubits.

• Phase-sensitive magnitude ($C_\mathrm{mag}$):

$C_\mathrm{mag} = \sqrt{W_X^2 + W_Y^2}$

Maximum achievable in the ideal case is $\sqrt{2} \approx 1.4142$.

• Inequality evaluation ($\mathcal{I}$): In the tripartite case, $2^3=8$ correlators $$E_{k_1k_2k_3} = \langle A_{k_1} B_{k_2} C_{k_3} \rangle$$ are estimated and combined to test bounds reflecting contextuality or observer dependence. The maximum theoretical value is $1.5$. Simulated and experimental values match theoretical expectations within statistical uncertainty (e.g., $\mathcal{I} = 1.498 \pm 0.009$ in simulation) (Ding et al., 2021).

5. Experimental Results and Device Constraints

Empirical benchmarks validate both the compilation strategy and the physical device. Representative outcomes include:

Metric	Ideal	Backend-Matched Sim.	Hardware Result
$V$	1.0000	0.9381	0.8771 ± 0.0034
$W_X$	1.0000	0.8984 ± 0.0031	0.8398 ± 0.0038
$W_Y$	-1.0000	-0.8972 ± 0.0031	-0.8107 ± 0.0041
$C_{\mathrm{mag}}$	1.4142	1.2697	1.1673 ± 0.0040

Device-calibrated noise models (including $T_1$, $T_2$, depolarizing CX errors, readout assignment) align closely with observed degradation in coherence witnesses, quantifying the impact of hardware imperfections. For instance, inserting a phase-flip channel of strength $\lambda$ on the “friend” register yields an expected witness attenuation of $(1-2\lambda)$, with experimental estimation yielding $\lambda_\mathrm{est}\approx0.080$ above the simulated noise floor—indicating off-diagonal sensitivity not captured by $V$ alone (Altman, 22 Jan 2026).

Typical device parameters during experimental runs:

• Single-qubit readout error: 3–5% per qubit
• CX gate error: 1.5–3$\times10^{-2}$
• $T_1,T_2$ times: 50–100 μs
• CX gate time: $\sim$350 ns

No active error-mitigation was applied; analysis is performed on raw shot statistics with propagated binomial uncertainties (Ding et al., 2021, Altman, 22 Jan 2026).

6. Reproducibility, Extension, and Scope

The pipelines for circuit compilation, simulation, calibration, execution, and analysis are fully open and reproducible. Scripts for circuit generation, backend calibration snapshot, noise simulation, and plotting are provided for both simulation and hardware phases, with all job IDs, SHA256 manifests, and calibration records archived in public repositories (Altman, 22 Jan 2026). This enables transparent benchmarking across devices and software versions.

The compiled circuit approach is generalizable to larger branch-divergence circuits, alternative hardware platforms, and error-mitigation strategies—including randomized compiling or zero-noise extrapolation. These methodologies allow progressively tighter experimental bounds on any hypothesized nonunitary signaling, providing a modular, operational basis for probing “inter-branch” phenomena.

Compiled Wigner’s-friend-style circuits do not constitute tests of quantum interpretations but instead yield reproducible operational constraints and serve as coherence-sensitive benchmarks of near-term quantum processors (Altman, 22 Jan 2026).