Violaris' Unitary Message-Transfer Primitive

• Violaris' Unitary Message-Transfer Primitive is a quantum-circuit protocol that conditionally transfers classical messages across branches in a coherent, Wigner’s-friend-style setup.
• It uses a fixed sequence of CNOT and Pauli-X gates to implement branch encoding, message writing, copying, and uncomputation, ensuring parallelizable operations and controlled circuit depth.
• Benchmark results across multiple superconducting architectures reveal message pattern-dependent performance, illustrating trade-offs between decoherence, compilers’ routing overhead, and circuit fidelity.

Violaris' Unitary Message-Transfer Primitive (UMP) defines a quantum-circuit protocol for effecting the conditional transfer of a classical message between "branches" in a Wigner's-friend-style circuit under coherent, globally unitary evolution. It provides an operational benchmark for inter-branch communication, with implementations on superconducting quantum hardware spanning up to $n=32$-qubit messages and multi-architecture comparisons. The UMP serves as both a hardware stress-test and a probe of decoherence, circuit compilation efficiency, and device-dependent error sources in near-term quantum processors (Cogburn, 27 Jan 2026, Altman, 22 Jan 2026).

1. Formal Definition and Operator Structure

The UMP is realized in a specific register ordering: $Q$ (the branch/measurement qubit) $\otimes$ $R$ (branch label/reference) $\otimes$ $F$ (friend’s state) $\otimes$ $M \equiv M_1 \ldots M_n$ (n-qubit memory) $\otimes$ $P\equiv P_1\ldots P_n$ (paper/message register). The ideal message-transfer unitary $Q$0 is a fixed composition of CNOT and Pauli-X gates:

$Q$1

with:

• $Q$2
• $Q$3
• $Q$4
• $Q$5
• $Q$6
• $Q$7

In compact operator form:

$Q$8

This ordering enforces strict sequential logic on message preparation, branch encoding, writing, copying, uncomputation, and final register swaps (Cogburn, 27 Jan 2026).

2. Gate-Level Decomposition and Two-Qubit Depth Scaling

In superconducting-device implementations (e.g., IBM Qiskit backends), the UMP circuit arranges the logical operations for efficient compilation within hardware connectivity constraints. For message size $Q$9:

• Top three wires: $\otimes$0, $\otimes$1, $\otimes$2 execute sequential CNOTs and single-qubit $\otimes$3 gates.
• Next $\otimes$4 wires ($\otimes$5): each receives a CNOT from $\otimes$6 (write), a CNOT to $\otimes$7 (copy), and a reverse CNOT from $\otimes$8 (uncompute).
• Bottom $\otimes$9 wires ($R$0): participate in pairwise (copy/uncompute) CNOTs.

The critical efficiency feature is that the $R$1 CNOTs in the copy/uncompute layers commute, supporting full parallelization for those stages. The overall two-qubit gate depth is:

$R$2

where $R$3 is set by the logical-to-physical mapping overhead of fanout from $R$4 to the $R$5 qubits. For message patterns with minimal Hamming weight ("sparse"), $R$6, yielding constant-depth circuits. For half-weight and dense patterns, $R$7, so depth grows linearly in $R$8 (Cogburn, 27 Jan 2026).

3. Message Families and Compilation Cost

The benchmarking campaign distinguishes three message patterns $R$9:

• Sparse (“one-hot”): $\otimes$0. Only one $\otimes$1 is flipped; $\otimes$2, compiled depth $\otimes$3 (constant).
• Half-weight: Randomly chosen positions, Hamming weight $\otimes$4; $\otimes$5, depth $\otimes$6.
• Dense (“all-ones”): $\otimes$7; all $\otimes$8 active, $\otimes$9, depth $F$0.

On planar superconducting topologies, every non-neighbor CNOT for half/dense families can require SWAP chains, inducing rapidly growing routing overhead. This leads to device- and compiler-seed-dependent variations: transpiler randomness at the coherence-depth frontier becomes a practical limitation for high-weight messages (Cogburn, 27 Jan 2026).

4. Performance Metrics and Diagnostic Observables

Performance evaluation of the UMP is postselected on $F$1 (the "message-receiver" branch). The key observables are:

• Bitwise success: $F$2
• String success ("all-bits"): $F$3
• Memory erasure after uncompute, postselected on $F$4: $F$5
• Branch contrast $F$6 on active bits: for $F$7,

$F$8

• Bitwise mutual information $F$9 (averaged over active bits):

$\otimes$0

where $\otimes$1 is the binary Shannon entropy.

These metrics diagnose both the strict string-level channel performance ($\otimes$2) and subtler correlations remaining under partial or noisy operation (e.g., $\otimes$3) (Cogburn, 27 Jan 2026).

5. Multi-Architecture Benchmarking Results

Benchmarks were obtained on IBM Eagle (ibm_rensselaer), Nighthawk (ibm_miami), and Heron r2/r3 (ibm_fez, ibm_boston) processors for $\otimes$4 up to $\otimes$5. No error mitigation was applied; all runs used 4096 shots and Qiskit transpiler level 3. Compilation variability was estimated for half/dense messages using randomized seeds.

Table: Maximum $\otimes$6 with $\otimes$7 (approximate values):

Backend	Dense	Half	Sparse
ibm_boston	24	32	32
ibm_fez	8	16	32
ibm_miami	16	24	32
ibm_rensselaer	4	8	24

Sparse-family $\otimes$8 at $\otimes$9:

• ibm_rensselaer $M \equiv M_1 \ldots M_n$0
• ibm_fez $M \equiv M_1 \ldots M_n$1
• ibm_miami $M \equiv M_1 \ldots M_n$2
• ibm_boston $M \equiv M_1 \ldots M_n$3

For half/dense messages, $M \equiv M_1 \ldots M_n$4 decreases roughly exponentially with $M \equiv M_1 \ldots M_n$5, illustrating the compounding effects of SWAP/routing-induced decoherence. A noteworthy result is that, for dense messages at $M \equiv M_1 \ldots M_n$6, $M \equiv M_1 \ldots M_n$7 spans from $M \equiv M_1 \ldots M_n$8 (ibm_rensselaer) to $M \equiv M_1 \ldots M_n$9 (ibm_boston).

Bitwise mutual information $\otimes$0 remains nonzero for dense messages even when $\otimes$1 at large $\otimes$2, signifying that some branch–message correlation persists despite an overall loss of string fidelity (Cogburn, 27 Jan 2026).

6. Hardware Noise, Error Sources, and Transpiler Variability

• Sparse family: Due to constant two-qubit depth ($\otimes$3), this regime serves as a controlled probe of device-dependent noise; hardware-to-hardware variability in $\otimes$4 at $\otimes$5 primarily reflects differences in intrinsic decoherence and CNOT fidelity.
• Half/dense families: Main limitation is SWAP/routing overhead. As the logical depth increases with message Hamming weight, both device connectivity and randomness in transpiler optimization yield large variations in circuit depth and $\otimes$6. Close to the coherence frontier, compiler-seed fluctuations can induce order-unity swings in success probability (Cogburn, 27 Jan 2026).

7. Amplitude Sweep, Divergence (“Cousins”) Sweep, and Channel Constraints

The UMP supports protocol-level stress tests probing channel linearity and complexity dependence:

• Amplitude sweep (no amplification test): By preparing $\otimes$7 to set $\otimes$8 and running $\otimes$9, one obtains $P\equiv P_1\ldots P_n$0. Empirically, the measured marginal weights perfectly track the ideal $P\equiv P_1\ldots P_n$1 relation across all tested backends, indicating no spurious amplification (Cogburn, 27 Jan 2026).
• Cousins-divergence sweep: A 16-qubit friend state is prepared with Hamming distance $P\equiv P_1\ldots P_n$2 between branches, adding $P\equiv P_1\ldots P_n$3 $P\equiv P_1\ldots P_n$4-gates to $P\equiv P_1\ldots P_n$5. At fixed $P\equiv P_1\ldots P_n$6, sweeping $P\equiv P_1\ldots P_n$7 from $P\equiv P_1\ldots P_n$8 to $P\equiv P_1\ldots P_n$9, the branch contrast $Q$00 falls linearly with $Q$01, reflecting increased circuit depth and cumulative noise.
• Channel constraints: In five-qubit (minimal) protocols, additional performance witnesses are defined:
  • Visibility $Q$02, extracted from $Q$03-basis readout.
  • Coherence witnesses $Q$04, $Q$05: multi-qubit parities in $Q$06 and $Q$07 bases, sensitive to off-diagonal coherence.
  • Phase-sensitive magnitude $Q$08.

Benchmarks on ibm_fez ($Q$09 shots) yield $Q$10, $Q$11, $Q$12, $Q$13, compared to ideal $Q$14. Visibility is primarily sensitive to population, while $Q$15 are directly attenuated by modeled dephasing channels: for $Q$16, a dephasing strength $Q$17 explains the observed reduction, setting the device constraint on coherence preservation (Altman, 22 Jan 2026).

• M. Violaris, “Quantum observers can communicate across multiverse branches,” (Violaris, 13 Jan 2026) (2026).
• C. V. Cogburn, "Inter-branch message transfer on superconducting quantum processors: a multi-architecture benchmark," (Cogburn, 27 Jan 2026) (2026).
• C. V. Cogburn, "Wigner's Friend as a Circuit: Inter-Branch Communication Witness Benchmarks on Superconducting Quantum Hardware," (Altman, 22 Jan 2026) (2026).