All-Transistor Probabilistic Computer

• All-transistor probabilistic computers are hardware systems that use CMOS-based p-bits with tunable randomness for efficient sampling and inference.
• They integrate analog and digital circuits—such as RNGs, weighted summation networks, and comparators—to emulate Bayesian and Ising-model computations with high energy efficiency.
• These architectures enable rapid combinatorial optimization and generative modeling, achieving significant speedup and energy savings over conventional CPU/GPU implementations.

An all-transistor probabilistic computer is a hardware architecture in which the fundamental unit of computation—the p-bit (probabilistic bit)—is realized entirely with CMOS (complementary metal–oxide–semiconductor) transistors. Each p-bit exhibits stochastic, tunable output behavior and is interconnected via transistor-based synapses to implement large-scale probabilistic networks, enabling efficient Bayesian inference, combinatorial optimization, and stochastic generative modeling. Unlike conventional digital logic, all-transistor probabilistic computers exploit controlled hardware randomness and analog nonlinearity at the transistor level, with architecture and algorithms co-designed for scalable, energy-efficient sampling from complex distributions (Jhonsa et al., 18 Apr 2025, Kaiser et al., 2021, Chowdhury et al., 2023, Jelinčič et al., 28 Oct 2025).

1. Underlying Device and Circuit Primitives

The p-bit is the hardware primitive embodying controlled stochasticity. Its output is a binary variable $m_i \in \{+1,-1\}$ (or {0,1}), with the instantaneous probability determined by a sigmoidal function of an analog input $I_i$: $P(m_i = +1) = \frac{1}{1+\exp(-2\beta I_i)}$ Typical all-transistor p-bit implementations require three principal subcircuits:

• Analog/Digital Random Number Generator (RNG): CMOS LFSRs (linear feedback shift registers) or subthreshold noise-based sources.
• Weighted Summation Network: Current-mode or digital MAC circuits compute $I_i = \sum_j J_{ij} m_j + h_i$; implementation options include R-2R DAC ladders, passive MOS resistor banks, and digital adder trees.
• Nonlinear Activation/Comparator: Fully differential comparators steer the summed input through a transfer function (tanh/sigmoid), often with injected noise for stochasticity. In analog variants, Winner-Take-All (WTA) blocks provide approximate tanh behavior (Jhonsa et al., 18 Apr 2025); in digital, LUTs or piecewise-linear functions are used (Kaiser et al., 2021, Chowdhury et al., 2023).

Transistor counts per p-bit range from $\sim 100$ (mixed analog-digital CMOS, as in current-mode designs) to $1000$–$5000$ (fully digital, high-reliability variant), depending on the complexity of the RNG and precision of the activation function. Ultra-compact architectures leveraging subthreshold shot-noise achieve $\sim 10$ transistors per RNG (Jelinčič et al., 28 Oct 2025).

2. Network Organization and Topology

Interconnection strategies depend on the target inference task:

• Ising-model and Boltzmann machines: Graph topologies (e.g., Chimera, two-colorable grids) are implemented via local, sparse couplings using analog current summation, digital SRAM-based weight storage, or programmable resistor networks (Jhonsa et al., 18 Apr 2025, Jelinčič et al., 28 Oct 2025).
• Chromatic Sampling and Clocking: Synchronous architectures utilize a global or two-phase clock tree; asynchronous architectures exploit local, free-running ring oscillators (ROSCs) or Poissonian clocks to drive each p-bit individually. Asynchronous kernel permits massive parallelism and mimics continuous-time Gibbs sampling (Aadit et al., 2022, Chowdhury et al., 2023).

The Chimera graph, as realized in (Jhonsa et al., 18 Apr 2025), comprises a $7 \times 8$ array of unit cells, with each p-bit connected to up to six neighbors, enabling both reciprocal (Boltzmann) and combinatorial-logic mappings.

3. Algorithmic Mapping and On-Chip Learning

All-transistor probabilistic computers implement statistical models directly in hardware:

• Ising Hamiltonians and QUBO: The energy function minimized is

$$H(\{s\}) = - \sum_{(i,j) \in E} J_{ij} s_i s_j - \sum_{i} b_i s_i$$

where $I_i$0. The system samples from $I_i$1 via hardware Gibbs sampling.

• Contrastive Divergence (CD): In-situ learning is realized by adjusting weights via

$I_i$2

with real-time hardware compensation for analog mismatch—empirical $I_i$3 vs. ideal is measured and weight/bias codes are firmware-corrected (hardware-in-the-loop learning) (Jhonsa et al., 18 Apr 2025).

• Diffusion-like Models: Architectures as in (Jelinčič et al., 28 Oct 2025) decompose denoising inverse problems as a chain of shallow EBMs, bypassing mixing-expressivity trade-offs for scalable generative modeling.

4. Performance Metrics and Benchmarking

Performance metrics include area efficiency, energy per p-bit update, sampling rate, and inference accuracy. Representative measurements:

• Area: $I_i$4 for 440 p-bits ($I_i$5) (Jhonsa et al., 18 Apr 2025).
• Power: $I_i$6 per p-bit ($I_i$7 total at $I_i$8).
• Sampling Rate: $I_i$9 per global clock step at $P(m_i = +1) = \frac{1}{1+\exp(-2\beta I_i)}$0–$P(m_i = +1) = \frac{1}{1+\exp(-2\beta I_i)}$1; ring-oscillator designs reach $P(m_i = +1) = \frac{1}{1+\exp(-2\beta I_i)}$2–$P(m_i = +1) = \frac{1}{1+\exp(-2\beta I_i)}$3 flip rates per p-bit (Aadit et al., 2022).
• Energy Efficiency: CMOS diffusion-like architectures reach $P(m_i = +1) = \frac{1}{1+\exp(-2\beta I_i)}$4 per cell/update, yielding $P(m_i = +1) = \frac{1}{1+\exp(-2\beta I_i)}$5 inference latency per image—$P(m_i = +1) = \frac{1}{1+\exp(-2\beta I_i)}$6 energy improvement over GPU-based models (Jelinčič et al., 28 Oct 2025).
• Task Accuracy: Correlation to ideal logic tables exceeds $P(m_i = +1) = \frac{1}{1+\exp(-2\beta I_i)}$7 for simple gates in $P(m_i = +1) = \frac{1}{1+\exp(-2\beta I_i)}$8 CD iterations; combinatorial optimization (MaxCut on 32-node graphs) produced solutions within $P(m_i = +1) = \frac{1}{1+\exp(-2\beta I_i)}$9 of optima in $I_i = \sum_j J_{ij} m_j + h_i$0 (Jhonsa et al., 18 Apr 2025).

5. Comparative Analysis and System-Level Trade-offs

Metric	All-Transistor Probabilistic Computer	GPU/CPU (Reference)
Energy/sample (FashionMNIST, DTM)	$I_i = \sum_j J_{ij} m_j + h_i$1 – $I_i = \sum_j J_{ij} m_j + h_i$2 J	$I_i = \sum_j J_{ij} m_j + h_i$3 J (DDPM), $I_i = \sum_j J_{ij} m_j + h_i$4 J (VAE)
Throughput	$I_i = \sum_j J_{ij} m_j + h_i$5 – $I_i = \sum_j J_{ij} m_j + h_i$6 s$I_i = \sum_j J_{ij} m_j + h_i$7	$I_i = \sum_j J_{ij} m_j + h_i$8 – $I_i = \sum_j J_{ij} m_j + h_i$9 s$\sim 100$0
Power consumption	$\sim 100$1 W (chip)	$\sim 100$2 W (A100 GPU)
FID (Gen. Modeling)	$\sim 100$3–$\sim 100$4 (chip)	$\sim 100$5–$\sim 100$6 (GPU)

Performance parity in generative modeling tasks is achieved at $\sim 100$7–$\sim 100$8 lower energy (Jelinčič et al., 28 Oct 2025). ASIC and FPGA p-computer prototypes consistently show $\sim 100$9–$1000$0 speedup in flips/sec over CPU/GPU for sparse Ising inference (Chowdhury et al., 2023).

6. Scalability, Limitations, and Architectural Extensions

Current scalability is bounded by device mismatch, interconnect sparsity, and analog component dynamic range. Notable bottlenecks and solutions are:

• On-chip device mismatch: Mitigated via frequent hardware-aware calibration (Jhonsa et al., 18 Apr 2025).
• Interconnect limits: Hierarchical tiling, 3D stacking, and adoption of sMTJ-based hybrid cells can extend scalability.
• Dense Synaptic Graphs: Challenge parallelism; sparsification strategies (COPY-gate embedding) are deployed but increase resource demand (Chowdhury et al., 2023).
• Energy Sharing and Technology Scaling: Further reductions by moving to advanced nodes (28 nm, 7 nm), with projections to $1000$1 spins/mm$1000$2 area densities.
• Expressivity vs. Mixing: Monolithic EBMs suffer from exponentially increasing mixing times with barrier height; diffusion-chain architectures (DTM) circumvent this via task decomposition (Jelinčič et al., 28 Oct 2025).
• Random Number Quality: High-quality local RNGs are critical, with subthreshold CMOS and sMTJs providing hardware entropy sources (Kaiser et al., 2021, Jelinčič et al., 28 Oct 2025).

Planned extensions include on-chip floating-gate or nonvolatile weight storage, adoption of alternative topologies (e.g., Pegasus), and integration of in-memory synapse crossbars for sparse and scalable matrix-vector multiplication.

7. Applications and Prospective Impact

All-transistor probabilistic computers have been validated experimentally for diverse tasks:

• Probabilistic Logic Emulation: AND gate and full adder realization, achieving high truth table fidelity in tens of CD iterations (Jhonsa et al., 18 Apr 2025).
• Combinatorial Optimization: MaxCut, ising spin-glass, 3-SAT, and knapsack problem solvers achieving four orders of magnitude improvement in time-to-solution over software baselines (Kaiser et al., 2021, Jhonsa et al., 18 Apr 2025).
• Bayesian and Markov-Logic Networks: Real-time sampling and marginal probability estimation for directed and undirected graph models (Behin-Aein et al., 2016).
• Quantum Monte Carlo Emulation: Efficient simulation of stoquastic Hamiltonians at classical hardware speeds, with sign-problem-free QMC approximately $1000$3 faster than CPU code (Chowdhury et al., 2023).
• Diffusion-based Generative Modeling: Energy-based denoising on image domains with near-GPU sample fidelity at $1000$4 energy budget (Jelinčič et al., 28 Oct 2025).

All-transistor probabilistic computation thus constitutes a technologically viable and energy-efficient paradigm for large-scale, hardware-accelerated stochastic computation, bridging physical device physics with high-level probabilistic inference and generative modeling.