Address-Event Representation (AER) Protocol

• AER protocol is an asynchronous communication scheme that encodes spike-like neural events as address packets with implicit timing.
• It uses a four-phase handshake, collision avoidance, and time-multiplexing to ensure reliable, low-power event transmission across complex networks.
• Applications include neuromorphic chips and event-driven vision sensors, achieving significant bandwidth reduction and scalable, energy-efficient hardware implementations.

The Address-Event Representation (AER) protocol is a class of asynchronous digital communication schemes widely implemented in neuromorphic and event-driven systems to transmit sparse, temporally precise spike-like events among computational elements such as neurons, cores, or chips. By encoding neuronal activity as discrete address-event packets—each signifying the occurrence and provenance of an event—the protocol achieves both efficient utilization of bandwidth and a natural mapping to biological-style communication wherein event timestamps are implicit in transmission timing. Rigorous handshake, collision-avoidance, and encoding schemes enable AER to scale across multi-core, multi-chip, and multi-node neuromorphic architectures while minimizing I/O pad count, silicon area, and dynamic power consumption (Qiao et al., 2019, Jose et al., 2020, Wang et al., 7 Apr 2026, R et al., 2023, Qiao et al., 2019).

1. Formal Definition and Protocol Mechanics

In standard AER, each event is defined as an ordered pair $e_k = (a_k, t_k)$, where $a_k$ is the address (usually a binary identifier of the source neuron or circuit) and $t_k$ is the event’s time of occurrence. Addresses are broadcast over a digital bus, while the event timing is encoded implicitly in the completion time of the bus handshake. A four-phase handshake protocol (request–grant–release–acknowledge) underpins event transfers, enforcing temporal causality and mutual exclusion:

• Data-Transfer Handshake: Sender asserts a request upon event generation; once the arbiter grants access, the sender places the address onto the bus, then releases the request and awaits acknowledgment, finalizing the cycle.
• Timing Extraction: The arrival time of a packet at its intended receiver (plus on-chip propagation delay) serves as the decoded event time.

Address-Event packets are stateless; no explicit counters or timestamps are required on the payload, as the interconnect guarantees that transmission delays are both bounded and reproducible (R et al., 2023, Jose et al., 2020).

2. Arbitration, Collision Avoidance, and Bus Multiplexing

Multiple event sources may simultaneously request access to the shared bus, necessitating arbitration to prevent contention:

• Arbiters: Asynchronous tree-structured mutex networks or cross-coupled NAND-based priority arbiters resolve concurrent events, ensuring only one sender accesses the bus per cycle (Wang et al., 7 Apr 2026).
• Collision Avoidance: State-machine-driven mode-switch handshakes (modeled as Mealy FSMs) with explicit control lines (e.g., SW_req, SW_ack) guarantee that at any instant, only one transmitter can drive the bus, while tri-state drivers physically isolate inactive ends (Qiao et al., 2019).
• Time-Multiplexing: Bi-directional communication is realized over a single parallel bus by dynamically switching drive-enable signals (TX_EN, RX_EN), with mode switches initiated and acknowledged in handshake cycles with direction switch latencies ≤ 5 ns (Qiao et al., 2019).
• Bus Encodings: Bundled-data schemes (with N-wide buses) or hierarchical binary tree encoders—assigning log₂N bits per event packet—further minimize wire count and energy per event (Wang et al., 7 Apr 2026).

3. Encoding Schemes and Compression

Fixed-Length and Sparse Encodings

In typical AER systems, the payload is a fixed-width binary word representing one or more active address indices. The standard encoding may be:

• One-hot code: For single-spike events—1 bit per neuron, exactly one set.
• Mask-based: For multi-spike events—a full N-bit vector, often highly sparse, resulting in poor bandwidth utilization under low activity (Jose et al., 2020).

Variable-Length Compression

Bandwidth inefficiencies under sparse and temporally correlated activity have motivated source coding solutions:

• Hawkes Process Model: Spiking behavior across N traces is modeled as a discrete-time Hawkes process, capturing both excitation and inhibition across traces over memory window τ.
• Context-Dependent Codebooks: At each event, the recent spiking state is used to generate a conditional codebook over possible address sets, enabling state-dependent Huffman-style encoding (Jose et al., 2020).
• Achievable Rates: The minimum average bit rate per event is given by

$$R^* = \sum_{s}\pi(s)\mathbb{E}_{P(\cdot\mid s)}\left[\left\lceil \log_2\left(\frac{r_s(I)}{2} + 1\right)\right\rceil\right]$$

where $\pi(s)$ is the stationary distribution of event states, and $r_s(I)$ the rank in probability.

Experimental results indicate that >60% reduction in wire bandwidth is feasible for realistic neuromorphic workloads when exploiting temporal and spatial spike correlations (Jose et al., 2020).

4. Asynchronous Implementation and Physical Realizations

Parallel Bus Transceivers

The bi-directional AER block by Qiao & Indiveri utilizes two nested four-phase handshakes and tri-state bus drivers in a 28 nm FDSOI process:

• Handshake Latency: 31 ns for a single data-transfer cycle, measured bidirectional throughput up to 28.6M events/s for 26-bit addresses.
• Scale and Energy: Each transceiver block occupies 140 µm × 70 µm and achieves 11 pJ/event dynamic energy (excluding I/O pads), with core dynamic tightly linked to bus capacitance and VDD (Qiao et al., 2019).
• I/O Pin Savings: Bi-directionality halves required I/O pads, reducing system complexity in large-scale tiled neuromorphic systems.

Bit-Serial LVDS Links

For high-speed inter-chip transmission, clock-less LVDS links employ Level-Encoded Dual-Rail (LEDR) coding with token-ring microarchitectures:

• Encoding: Each bit is mapped onto two wires (data, parity) alternating odd/even DI phases; no DLL/PLL or clock recovery is needed.
• Wake/Sleep: Event-driven CM feedback enables automatic ON/OFF of line drivers, achieving sub-μA idle current and 31 ns event round-trip latencies at 1.5 Gb/s bit rate for 32-bit events (Qiao et al., 2019).
• Scaling: The design supports linear scaling of power with event rate and achieves 35.7 M events/s at peak throughput.

Ultra-low-power Synthesizable Encoders

Tree-based architectures, implemented in digital standard cells, offer fully synthesizable, low-latency AER encoding:

• Micropipeline: Semi-decoupled, four-phase handshakes using edge-triggered flip-flops enable high-throughput, standard EDA compatibility, and rapid place-and-route.
• Arbitration: Per-node stochastic priority using cross-coupled NANDs ensures fair, metastability-resilient encoding.
• Performance: 33 M events/s (8-input prototype), 50 ns mean event latency, and 435 fJ/event total energy (Wang et al., 7 Apr 2026).

5. Programmable Interconnects and Temporal Computing

AER protocols natively support temporal causality primitives:

• Delay: Routing is implemented by explicit temporal delays in event delivery, either via FIFO structures or time-multiplexed channels.
• Triggering: Hardware comparators enforce arrival deadlines, serving as temporal filters.
• Sorting: Request arbitration inherently sorts events by timestamp, ensuring causally ordered delivery (R et al., 2023).

The Time-to-Event Margin Propagation (TEMP) methodology actively exploits AER's temporal nature:

• Computing with Delays: Synaptic weights are replaced by configurable path delays, with neuron activation defined by cumulative temporal margins.
• No Local MAC: Local multiply-accumulate is replaced by “weight-as-delay” mappings in routing tables.
• Energy and Memory Implications: The combination of programmable interconnect, delay-based arithmetic, and asynchronous transport collapses traditional memory and compute structures, enabling sparse computation and scalable hardware (R et al., 2023).

6. Performance, Scalability, and Applications

Table: Representative Performance Metrics of Recent AER Implementations

Architecture	Process/Tech	Throughput	Event Latency	Energy/Event
Bi-directional AER (Qiao & Indiveri)	28 nm FDSOI	28.6 M Ev/s	31 ns	11 pJ (26-bit)
LVDS LEDR Link	0.18 µm CMOS	35.7 M Ev/s	31 ns	– (19.3 mA peak Rx)
Synthesizable Tree Encoder	65 nm CMOS	33 M Ev/s	50 ns	435 fJ

AER protocols are foundational in event-driven vision sensors, spike-based neural networks, and large-scale neuromorphic chips where efficient, low-latency, and energy-proportional interconnect is critical. The scalability of both parallel and serial AER fabrics—ensured by mutual-exclusion handshakes, collision-free arbitration, and bundled-data protocols—aligns with the stringent requirements of edge devices and massive neural hardware arrays (Qiao et al., 2019, Wang et al., 7 Apr 2026, Qiao et al., 2019).

7. Limitations, Trends, and Research Directions

Current AER implementations face several challenges:

• Arbiter Complexity: Bus arbitration scales with the number of sources and increases wire/logic demand. As system size grows, tree-structured or hierarchical arbiters are required (Wang et al., 7 Apr 2026).
• Payload Bandwidth: Fixed-length, sparse encodings underutilize available serial bandwidth unless advanced compression is deployed (Jose et al., 2020).
• Delay Calibration: Fine-grained delay-based computation requires precise timing calibration, considering silicon variability, temperature, and device aging (R et al., 2023).
• Routing Table Growth: Programmable, multi-bit delay routing schemes sharply increase memory requirements, necessitating compression or hierarchical strategies.
• Physical I/O Constraints: I/O pin count and pad capacitance constrain throughput for massively parallel buses, motivating further innovation in multiplexed and serial protocols (Qiao et al., 2019, Qiao et al., 2019).

Ongoing research addresses these limitations through innovations in variable-length compression, ultra-low-power asynchronous serial link design, synthesizable digital AER encoders, and architectures that exploit interconnect delays as computational substrates. These advances extend the applicability of AER far beyond passive spike routing, positioning it as a critical technology for future neuromorphic and time-domain computing platforms (Jose et al., 2020, R et al., 2023, Wang et al., 7 Apr 2026).