Hybrid Analog-Digital CIM Architectures

• Hybrid analog-digital CIM architectures are data-centric systems that integrate analog MACs with digital quantization to balance precision, energy, and area.
• They employ diverse schemes such as MSB–Digital/LSB–Analog partitioning, charge-domain collaboration, and capacitor reconfiguration to optimize performance.
• These systems are pivotal for accelerating deep neural networks, matrix operations, and optimization tasks by enabling efficient hardware-algorithm co-design.

Hybrid analog-digital compute-in-memory (CIM) architectures leverage both the intrinsic efficiency of analog computation and the digital domain’s precision and programmability, seeking optimal trade-offs among area, energy, speed, and computation accuracy for data-intensive workloads such as deep neural networks (DNNs), matrix operations, and constrained optimization. These architectures integrate analog multiply-accumulate (MAC) operations directly in memory arrays with digital quantization, accumulation, and control, spanning a large and rapidly evolving design space—comprising cell-level circuit innovations, architectural reconfigurations, adaptive precision schemes, and system-level co-design with algorithms.

1. Principles and Taxonomy of Hybrid Analog-Digital CIM

Hybrid analog-digital CIM is rooted in the desire to combine the strengths of analog CIM (ACIM)—high area and energy efficiency for low-to-medium precision (3–8 bits) MACs—with the bit-true accuracy and robustness of digital CIM (DCIM). Pure ACIM designs are limited by non-idealities (thermal noise, device mismatch, finite ADC quantization), while pure DCIM incurs prohibitive area and energy cost in adders or multipliers as precision increases. Hybrid approaches exploit clear partitionings:

• MSB–Digital/LSB–Analog Partitioning: Most significant bits of inputs/weights are routed to a digital adder tree (or digital sub-array), while least significant bits (LSBs) use analog MACs plus ADC conversion. The final result is recombined digitally as $y_\text{total} = y_\text{MSB} + y_\text{LSB}$ (Yoshioka et al., 2024, Konno et al., 25 Aug 2025).
• Charge-Domain Collaborative Digitization: Arrays collaborate, such that some serve as analog MAC generators and others provide in-situ digitization references, folding ADC and DAC circuits into the memory fabric (Nasrin et al., 2023).
• Capacitor-Reconfiguring Schemes: Arrays reuse the same capacitor network for both MAC charge accumulation and as SAR-ADC DACs via reconfigurable switches (Yoshioka, 2023).
• Data-Adaptive/Saliency-Aware Digitization: Precision is dynamically allocated based on data importance, either at run-time (“saliency-aware” boundary allocation) or statically via pre-trained thresholds (Chen et al., 2023).
• Co-Integrated Floating-Point Hybridization: Digital logic handles exponent and MSB mantissa components, while analog logic implements high-throughput sub-multiplications on the mantissa (Yi et al., 11 Feb 2025).
• 3D Hybrid Integration: Combining SRAM (fast, digital-friendly) and eDRAM (area/energy-efficient, analog-friendly) via vertical monolithic integration allows distinct function partitioning for general matrix operations (Chakraborty et al., 15 Apr 2026).

This taxonomy is reflected in both academic and commercial designs, with system-level trade-offs between precision, parallelism, energy, and area being explicitly characterized.

2. Circuit-Level Innovations and Topologies

A representative hybrid CIM array employs the physical structure of CMOS SRAM (typically 6T or 8T), often with augmentations:

• Parasitic Capacitance DAC/ADC: The unused parasitic capacitances on SRAM columns/bit-lines are harnessed to form local DAC ladders or reference caps. Arrays precharge their bit-lines in binary patterns to establish reference voltages. Proximal arrays alternate between analog sum generation and reference driving (Nasrin et al., 2023).
• Composable Capacitor Arrays: Custom bit-cell layouts with attached metal–insulator–metal (MOM) fringe capacitors or 2D-weighted capacitor matrices support matrix operations on both real and imaginary axes of complex numbers (Konno et al., 25 Aug 2025).
• Capacitor-Reconfiguring MAC/ADC: The same physical cap array serves for both charge storage during accumulate and, via re-switching, as the SAR-ADC’s capacitive DAC, eliminating the signal attenuation inherent in dumping charge out to external arrays (Yoshioka, 2023).
• Split-Port SRAM for Dual-Mode MAC: Dual sets of bit-lines and word-lines allow simultaneous digital (logical) and analog (charge-based) MAC operations, enabling granular sub-array reconfiguration without additional peripheral circuits; the digital-to-analog boundary is programmably selectable per cycle (Chen et al., 2023).
• Charge-Based Screening: Analog MACs rapidly compute coarse results (e.g., 4 MSB-level dot products for attention pruning), while only a small subset of results is forwarded for precise digital recomputation, exploiting sparsity in real-time (Moradifirouzabadi et al., 2024).
• Comparator-Chain Digital Arrays: In ADC-less hybrids, comparators replace per-column ADCs; quantized outputs are immediately processed in digital arrays storing trainable scale factors (Negi et al., 2024).

These innovations are typically integrated into hierarchical architectures with tiled arrays, buffers, and inter-array networking for scalable parallelism.

3. Operational Workflows and Interface Protocols

Hybrid CIM’s pipeline is characterized by alternating analog and digital domains at several granularities:

• Bit/Bit-Group Partitioning: Upper bits routed to digital MAC trees, lower bits to analog accumulation; digital post-processing sums both (Yoshioka et al., 2024, Konno et al., 25 Aug 2025).
• Stepwise SAR/Flash ADC: In-memory analog results are digitized by hybrid ADCs employing a mixture of fast Flash steps for MSBs and SAR iteration for LSBs, implemented via in-memory DAC ladders (Nasrin et al., 2023).
• Dynamic Precision Selection: Data saliency or importance is estimated via rapid digital MACs. A boundary register is updated, controlling which bits (or bit orders) are computed by which domain (Chen et al., 2023).
• Floating-Point MACs: Digital exponent addition and mantissa alignment precede hybrid sub-ADD (digital) and sub-MUL (analog). Cursor-charging stores analog product, which is digitized by low-resolution flash ADCs (Yi et al., 11 Feb 2025).
• Analog–Digital Joint Dataflow: Analog dot product or convolution results are digitized and subsequently accumulated/summed digitally—either within memory using in-place adders or in a downstream processor (Yoshioka, 2023, Negi et al., 2024).

The analog–digital crossover is managed by state machines, FSMs, and clock-driven control—ensuring read/write, precharge, compute, and conversion phases are orchestrated for both throughput and correctness.

4. Performance Metrics and Quantitative Trade-offs

Hybrid analog-digital CIM architectures are evaluated against several quantitative metrics:

• Area and Energy: Memory-immersed ADCs can yield $25\times$–$51\times$ area savings and $1.4\times$–$13\times$ energy savings over conventional 5-bit SAR or Flash ADCs (Nasrin et al., 2023). Full hybrid complex-CIM yields single-cycle complex MACs at 35 TOPS/W and 1.80 Mb/mm², substantially exceeding pure DCIM or ACIM in density and energy (Konno et al., 25 Aug 2025).
• Precision and SNR: Effective precision is modulated by the analog/digital boundary and converter resolution. Layer-adaptive majority voting in the SAR-ADC stage can provide $+5.5$ dB CSNR at $+1.9\times$ power, valuable for high-accuracy layers in transformers (Yoshioka, 2023). Measured INL/DNL below 0.5 LSB ensures <1% classification degradation for 5-bit hybrid schemes (Nasrin et al., 2023).
• Throughput and Parallelism: ADC bottlenecks are alleviated by embedding conversion in the array or by extreme low-precision quantization (e.g., ternary MACs), permitting full array parallelization (Negi et al., 2024, Nasrin et al., 2023).
• Algorithm–Hardware Co-Design Impact: In ADC-less hybrid designs, training with quantization-aware algorithms permits direct ternary MAC computation in analog, with digital correction via scale factors, yielding up to $28\times$ energy savings versus 7-bit ADC CIM baselines at modest accuracy loss (Negi et al., 2024).
• Dynamic Precision/Efficiency Trade-off: Saliency-aware CIMs dynamically allocate resources, achieving $1.95\times$ better TOPS/W than full DCIM at application accuracy loss of 0.1–4.8% (configurable) (Chen et al., 2023).
• Domain-Specific Metrics: For transformer attention, hybrid charge-based screening of low-score tokens reduces digital MAC load by $\sim$75%, with system-level energy efficiency up to 14.8 TOPS/W and area efficiency up to 976.6 GOPS/mm² at <0.4% application accuracy loss (Moradifirouzabadi et al., 2024).
• Generalized Matrix Operations: 3D-stacked hybrid CIM expands capability to include element-wise addition, multiplication, and transpose, achieving $25\times$0 GOPS/W with effective compute density of 0.5 TOPS/mm² (Chakraborty et al., 15 Apr 2026).

Summary Table:

Architecture	Area Eff.	Energy Eff.	Precision (typ.)	Notable Results
Mem-immersed hybrid CIM (Nasrin et al., 2023)	25–51× vs. ADC	1.4–13× vs. ADC	5–6 bits	INL/DNL < 0.5 LSB, <1% acc. drop on MNIST
CR-CIM (Yoshioka, 2023)	–	818 TOPS/W	10 bits (SAR-ADC)	4× comparator energy reduction
Complex hybrid CIM (Konno et al., 25 Aug 2025)	1.80 Mb/mm²	35 TOPS/W	8 bits complex MAC	0.435% RMS error, single-cycle C-MAC
OSA-HCIM (Chen et al., 2023)	–	5.79 TOPS/W	Up to 8 bits dynamic	Adaptive B_{D/A}, <2% acc. drop
ADC-less HCiM (Negi et al., 2024)	–	28× vs ADC-CIM	Ternary MACs	Fully parallel, digital scale-factor acc.
3D GEM3D-CIM (Chakraborty et al., 15 Apr 2026)	0.5 TOPS/mm²	430 GOPS/W	4 bits	In-memory transpose, add, mult (>2× vs. 2D)

5. Application Domains and Algorithm–Hardware Co-Design

Hybrid CIM architectures are deployed in a wide array of DNN and signal processing workloads:

• Deep Neural Network Inference: Area and energy-efficient acceleration of CNNs, transformers, and SSMs, particularly when moderate-precision (6–8 bits) suffice (Yoshioka et al., 2024, Yi et al., 11 Feb 2025).
• Transformers and Attention: CR-CIMs and capacitor-reconfiguring hybrid arrays reach 10-bit precision with low-variance noise under software–analog co-design, while attention-specific hybrids combine analog screening with digital post-selection (Yoshioka, 2023, Moradifirouzabadi et al., 2024).
• Complex-Valued Operations: Hybrid complex-number macros with 2D capacitor arrays support DSP and communications (e.g., channel equalization, FFT/IFFT) (Konno et al., 25 Aug 2025).
• Hybrid Projection in SSMs: Output projections in SSMs are performed as a product of rank-reduced analog and digital multiplies (via SVD), dramatically increasing robustness to device noise while keeping analog energy savings (Feng et al., 16 Aug 2025).
• General Matrix Computation: GEM3D-CIM extends in-memory computation to general-purpose matrix algebra—including transpose and element-wise ops—enabling LSTM/GRU, PDE solvers, and masking/attention with 3D stacking (Chakraborty et al., 15 Apr 2026).
• Photonic/Quantum Optimization: In hybrid measurement–feedback coherent Ising machines (MF-CIM), optical analog hardware is combined with digital FPGA-based feedback (via ADC/DAC), illustrating bottlenecks and foundational trade-offs specific to photonic CIM (Khosravi et al., 19 Jul 2025).

Co-design with quantization-aware, saliency-prioritized, or projection-partitioned algorithms is critical, with performance and efficiency gains sensitive to workload, layer, and partition boundaries.

6. Challenges, Limitations, and Emerging Directions

• Analog Non-Idealities: Noise, device mismatch, and temporal drift fundamentally limit effective precision for analog MAC to about 6–8 bits before digital supplementation is required (Yoshioka et al., 2024).
• ADC/DAC Bottlenecks: Area and latency overhead scale exponentially with converter resolution; hybrid approaches embedded in array parasitics or leveraging extreme quantization mitigate but do not eliminate these costs (Nasrin et al., 2023, Negi et al., 2024).
• Complexity of Dynamic Boundaries: Fine-grained data-adaptive boundaries (e.g., saliency-aware digital/analog switching) impose system-level timing, control, and design verification burdens (Chen et al., 2023).
• Calibration and Testing: Layout and matching of ultra-small capacitors, as well as runtime offset or gain correction, are nontrivial and require dedicated calibration phases or proprietary techniques (Konno et al., 25 Aug 2025).
• Scalability of Integration: 3D monolithic or MIV-based vertical integration compounds process complexities, though it unlocks high compute density and in-memory data movement (Chakraborty et al., 15 Apr 2026).
• Algorithm–Hardware Interplay: Hybrid designs often rely on tailored network training (e.g., partial sum quantization, SVD-based decomposition) that must be supported by the machine learning software stack and toolchain (Feng et al., 16 Aug 2025).
• Optical and Quantum Domain Bottlenecks: In hybrid photonic CIM, iterative measurement–feedback with digital processing creates latency and power bottlenecks that only fully analog photonic integration can overcome (Khosravi et al., 19 Jul 2025).

Key emerging directions include co-optimized data-aware hybridization (e.g., for LLMs), broader adoption in non-volatile memory arrays (ReRAM, PCRAM), progressive scaling of array sizes, dynamic precision allocation via run-time workload analysis, and full-stack integration into AI-specific SoCs.

7. Outlook and Impact

Hybrid analog-digital CIM approaches constitute a pivotal direction in data-centric hardware, striking an operational balance between throughput, precision, area, and power. Through embedding analog MAC where device physics permits, fusing it with digitally controlled quantization and accumulation, and adapting precision at per-layer or per-operation granularity, hybrid CIM enables next-generation AI acceleration—supporting dynamic, context-dependent tasks without incurring the prohibitive barriers of either pure digital or pure analog implementations. Future deployments in edge-AI, cloud inference, wireless DSP, and general-purpose high performance computing are poised to expand as developments in calibration, control, and toolchain support further mature the ecosystem (Nasrin et al., 2023, Yoshioka, 2023, Yoshioka et al., 2024, Konno et al., 25 Aug 2025, Negi et al., 2024, Chen et al., 2023, Khosravi et al., 19 Jul 2025, Feng et al., 16 Aug 2025, Yi et al., 11 Feb 2025, Chakraborty et al., 15 Apr 2026, Moradifirouzabadi et al., 2024).