CAKE: Compiler-Agent Co-Design for Frontier Kernel Evolution

Abstract: GPU kernel agents and GPU programming languages have advanced separately, leaving expert kernels difficult to reproduce. Agents usually treat the compiler as a fixed black box and receive only errors, correctness outcomes, and timing, while existing DSLs either hide critical scheduling decisions or expose them through difficult layout abstractions. We present CAKE, a compiler-agent co-design in which agents author CAKE IR, a typed, hardware-explicit schedule representation. CAKE exposes warp roles, memory movement, synchronization, and pipelines while supporting verification, cost modeling, and localized diagnostics. The harness itself evolves: recurring failures become verifier rules, IR primitives, model calibrations, and reusable optimization tactics. In matched implementation-hidden Flash-KMeans clean starts on B200, the best CAKE IR candidate at an 80-million-token budget runs at 1.144x the tuned FlashML baseline, compared with 0.928x for direct CUDA/PTX. Beyond this benchmark, agent-generated Kimi Delta Attention achieves a 2.05x geometric-mean speedup over official FlashKDA and passes end-to-end serving validation. Dispatcher-backed KNN and KMeans improve performance by 1.42x to 2.12x across more than 400 shapes, and four kernel changes are available as upstream PRs. CAKE targets NVIDIA GPUs from Ampere through Blackwell and separates single-shape evolution from library generalization and dispatch.

• The paper introduces Cake IR and an evolving compiler harness that expose warp roles, pipelines, synchronization, and memory placement while automating mechanical GPU lowering and diagnostics.
• The paper reports strong results, including 1.144× median Flash-KMeans baseline attainment, 2.05× geometric-mean Kimi Delta Attention speedup, and 10 of 11 known-kernel results meeting or exceeding references.
• The paper shows how compiler feedback can become reusable infrastructure through verifier rules, cost-model calibration, lowering improvements, and dispatcher-backed kernel portfolios, while noting limitations in portability and ablation coverage.

CAKE: Compiler–Agent Co-Design for Frontier Kernel Evolution

Research Problem and Central Thesis

“CAKE: Compiler-Agent Co-Design for Frontier Kernel Evolution” (2608.12629) addresses a structural limitation in automated GPU-kernel optimization: kernel-generation agents typically search over programs while treating the compiler, intermediate representation, diagnostics, and hardware model as fixed infrastructure. This design constrains the search process precisely where expert kernel development depends on information that ordinary compiler feedback does not expose.

Conventional agentic kernel optimization returns a relatively narrow feedback signal: compilation success or failure, numerical correctness, and end-to-end latency. These observations are insufficiently causal. A synchronization failure does not necessarily identify the violated producer–consumer contract; a hardware-conformance failure may not reveal the incompatible instruction or resource; and a latency measurement does not isolate whether the limiting factor is memory movement, pipeline depth, warp-role imbalance, instruction admission, or synchronization overhead. The result is an optimization loop in which agents repeatedly rediscover low-level constraints rather than accumulating reusable compiler knowledge.

CAKE proposes that the representation being searched and the compiler harness providing feedback should evolve together. Its core thesis is that agentic kernel optimization requires a typed, hardware-explicit schedule IR with localized static diagnostics, while the IR, verifier, lowering rules, and cost model must themselves improve in response to recurring kernel-development failures.

The resulting system separates three forms of evolution. Kernel evolution searches for better schedules for a workload. Compiler evolution adds abstractions, legality rules, lowering support, and model calibrations when the search exposes missing capabilities. Portfolio evolution converts specialized single-shape kernels into dispatcher-backed families suitable for library integration.

Architecture of the Co-Design System

CAKE exposes Cake IR as the agent-facing representation and lowers it to CUDA/PTX for execution. Unlike high-level tile DSLs, Cake IR makes warp specialization, asynchronous memory movement, buffer staging, synchronization, and memory-tier placement explicit. Unlike CUDA or PTX, it avoids requiring the agent to author mechanical details such as barrier addresses, phase bits, descriptor encodings, tensor-memory offsets, and warp identities.

The design is organized around typed operations, declared resources, explicit warp roles, and compiler-derived metadata. Programs declare shared-memory and tensor-memory regions, synchronization objects, pipelines, and warp groups. Operations are drawn from a fixed vocabulary covering computation, memory movement, synchronization, and control. Every cross-role handoff is represented explicitly, which allows the compiler to relate diagnostics to a concrete resource, pipeline stage, or scheduling decision.

Cake IR intentionally does not expose layout as an independent algebraic abstraction. The agent instead specifies concrete storage and access commitments—such as shared-memory views, offsets, tensor-memory ranges, swizzle annotations, and transfer coordinates—while the compiler checks their compatibility along the dataflow and against target-specific instruction contracts. This is a significant and deliberately contradictory design choice relative to contemporary low-level GPU DSLs: CAKE increases hardware explicitness while removing layout algebra from the agent’s editing interface.

The abstraction is designed to span NVIDIA architectures from Ampere through Blackwell. Structural schedule concepts such as roles, barriers, and pipelines are shared across targets, whereas instruction selection, resource legality, and lowering remain architecture-specific. The compiler requires an exact target match and reports unsupported device features rather than silently substituting a different execution model.

Figure 1: CAKE’s architecture couples kernel evolution, structured compiler evidence, and an outer compiler-evolution loop.

Evidence-Driven Compiler Evolution

The paper’s principal systems contribution is not merely a new DSL, but an evolving compiler harness. The harness performs pre-compilation safety and conformance checks, numerical validation against an external oracle, performance modeling, and on-device profiling. Static checks cover synchronization, memory safety, dataflow, resource use, instruction availability, representation compatibility, and schedule invariants.

The diagnostics are intended to be actionable rather than merely classificatory. A candidate can be rejected with a localized finding tied to a program region or hardware contract. Performance reports provide bottleneck classes and optimization guidance, although GPU measurement remains authoritative. The cost model ranks and filters candidates before expensive execution; it does not replace empirical timing.

Repeated failure modes are treated as evidence for compiler changes. A runtime crash may become a verifier rule. A recurring illegal-lowering pattern may motivate a new static analysis. A systematic cost-model error may generate a calibration task. A kernel schedule that cannot be expressed may require a new IR primitive or resource type. These changes are corpus-tested because the paper treats syntax, effects, legality, and analyses as a coupled system rather than independent compiler components.

Figure 2: Corpus and runtime evidence are routed into validated changes to the verifier, IR vocabulary, lowering system, and performance model.

This mechanism changes the effective learning dynamics of the agent. Instead of storing every failure as an isolated textual observation, the system attempts to convert recurrent failures into reusable infrastructure. The compiler harness therefore becomes a persistent domain-specific memory whose contents are executable: legality rules, typed constructs, lowering implementations, calibration data, and regression tests.

Agent Workflow

CAKE’s workload contract fixes the mathematical specification, input shapes, correctness oracle, tolerances, target hardware, and permitted references. Within that contract, the agent proceeds through four stages.

First, it generates structurally distinct Cake IR candidates. Second, candidates undergo IR-construction checks, verifier gates, and cost-model ranking before GPU execution. Third, surviving candidates are compiled, numerically validated, benchmarked, and profiled. Fourth, the resulting evidence is routed to the candidate schedule, verifier, cost model, or IR vocabulary according to the diagnosed failure.

This division is important because it decouples cheap rejection from expensive empirical evaluation. It also makes optimization decisions auditable: retained candidates, diagnostic reports, benchmark outcomes, and compiler changes form a persistent record rather than an opaque sequence of agent edits.

The evaluation holds the model and agent scaffold fixed, using GPT-5.6-sol at xhigh reasoning effort. Consequently, the reported comparisons are intended to measure the effect of the representation and environment rather than improvements in model capability.

Clean-Start Flash-KMeans Evaluation

The most controlled experiment compares Cake IR with direct CUDA/PTX generation on a fixed Flash-KMeans assignment kernel. The agent is given the workload specification, correctness oracle, and benchmark interface but cannot inspect low-level target implementations. The target is a B200 GPU, with $B=32$, $N=65{,}536$, $K=1024$, and $D=128$, using BF16 inputs and FP32 accumulation. Performance is normalized to a tuned FlashML Triton implementation with a measured latency of $0.938$ ms.

The experiment uses three matched runs per representation and an 80-million-token budget. CAKE reaches a median best performance of $1.144\times$ the tuned FlashML baseline, with a run range of $1.041\times$–$1.205\times$. Direct CUDA/PTX reaches only $0.928\times**, with a range of$0.852\times$–$1.151\times$$. Cake IR satisfies the paper’s plateau criterion in **3/3 runs</strong>, whereas direct CUDA/PTX satisfies it in <strong>0/3 runs</strong>. Median active evolution time is also lower: <strong>1.89 hours</strong> for Cake IR versus <strong>3.73 hours</strong> for CUDA/PTX.</p> <p>The trajectory is as important as the endpoint. The mean Cake IR population crosses the tuned baseline at approximately 55 million tokens and continues improving. The direct CUDA/PTX population remains below the baseline at the 80-million-token cutoff. These results support the claim that structured diagnostics and a constrained but hardware-explicit representation improve search efficiency, not merely the final attainable kernel quality.</p> <p>However, the experiment remains narrow. It measures one fixed shape, one workload component, one GPU generation, and one agent scaffold. It demonstrates a meaningful representation effect, but does not establish universal superiority over CUDA/PTX or quantify how much performance derives from the current compiler implementation rather than the IR abstraction itself.</p> <h3 class='paper-heading' id='frontier-kernel-synthesis'>Frontier-Kernel Synthesis</h3> <p>The frontier-kernel experiments test whether agents can discover effective physical schedules without access to low-level target implementations.</p> <p>For Kimi Delta Attention, the generated prefill implementation achieves a <strong>$$N=65{,}536$0 geometric-mean speedup over official FlashKDA across six B200 BF16 shapes. It is bitwise correct on the validation contract and is validated in end-to-end Kimi-K3 serving under SGLang. The separate decode paths achieve a $N=65{,}536$1 geometric-mean speedup over upstream FlashInfer across 30 public-API shapes. KDA is a demanding target because its recurrent state must remain live across chunks, requiring coordination among persistent state, memory movement, and pipeline scheduling.

CAKE also produces improved Gated DeltaNet and MiniMax sparse-attention paths, demonstrating that the representation is not limited to conventional GEMM-like operators. These are dispatcher families composed of multiple Cake IR programs behind a logical interface, rather than single kernels specialized to one benchmark point.

In TinyGEMM evolution, starting from a production small-$N=65{,}536$2 BF16 kernel, agents generate adaptive shallow- and deep-pipeline variants, including programmatic dependent launch variants and batch-size-specific paths. The resulting family reduces geometric-mean kernel time by 18–23% across 35 canonical shapes. The associated serving experiment reports up to 7.6% higher output throughput for GPT-OSS-120B at concurrency 128 on TP1, while TP4 differences remain within measurement noise.

The Alpha-MoE case evaluates communication-rich fusion. CAKE agents rewrite a Hopper-oriented W8A8 fused MoE megakernel for Blackwell, combining routed gather, two projections, activation, requantization, and weighted output accumulation. Relative to a TensorRT-LLM-derived pre-routed API, the reported API-level speedups are $N=65{,}536$3 at $N=65{,}536$4 and $N=65{,}536$5 at $N=65{,}536$6. GPU-span remeasurement gives the more conservative $N=65{,}536$7 and $N=65{,}536$8 improvements, respectively. The gap between these measurements reflects launch and scheduling overhead: the reference executes five GPU activities, while the fused implementation uses an output reset and a single megakernel.

These results show that the system can discover schedules involving asynchronous transfers, persistent state, warp-role partitioning, and inter-kernel fusion. They also reveal the importance of carefully defining denominators. API-level speedups can include launch and orchestration effects, whereas GPU-span speedups isolate device execution more narrowly.

Reproduction of Established Kernels

The known-kernel evaluation addresses a different question: whether CAKE can preserve or improve expert schedules when reference implementations are available. The tested families include attention forward and backward, decode kernels, low-precision GEMM, MQA indexers, MLA decode, and sparse MLA paths, with references drawn from TensorRT-LLM, CUTLASS, DeepGEMM, FlashAttention-4, and FlashInfer.

Across eleven fixed comparisons, ten meet or exceed their listed reference, while the remaining result reaches 96.5% of the reference. The strongest improvements are the FP8 and FP4 MQA indexers, at approximately $N=65{,}536$9. A CUTLASS MLA decode variant reaches $K=1024$0, while the two FlashAttention-4 comparisons reach $K=1024$1 and $K=1024$2.

The paper appropriately qualifies these results. Below-reference variants often indicate incomplete compiler integration rather than an algorithmic disadvantage. Above-reference variants are not necessarily faithful translations; the agent may discover schedule changes absent from the original implementation. The reported compactness of Cake IR is similarly descriptive rather than a language-independent productivity claim, since line-count scopes and semantics differ across implementations.

From Specialized Kernels to Library Portfolios

A central methodological contribution is the explicit separation between single-shape optimization and library-level generalization. Optimizing one exact shape rewards aggressive specialization and provides a clean performance denominator. A serving library, by contrast, must handle an open shape distribution, dispatch overhead, tail cases, guard interactions, and fallback behavior.

CAKE therefore treats generalization as a second optimization stage. Strong single-shape seeds are grouped into shape buckets, specialized or shared variants are constructed, and guards are ordered behind an explicit fallback. Validation includes held-out shapes, boundary cases, tail conditions, overlapping or missing predicates, and the fallback route. The valid shape domain is declared before tuning to prevent dispatcher predicates from introducing evaluation leakage.

On GB200, dispatcher-inclusive results report geometric-mean GPU-span speedups of $K=1024$3 across 112 KNN-build shapes, $K=1024$4 across 198 KNN-search shapes, and $K=1024$5 across 124 Flash-KMeans shapes. KNN achieves recall 1.0 with no incorrect outputs. These measurements must not be conflated with the fixed-shape Flash-KMeans clean-start result: the hosts, shape distributions, baselines, and protocols differ.

The portfolio design also imposes a complexity discipline. A new physical schedule is introduced only when the shape domain requires a material scheduling change, and dispatcher complexity must be justified by measured workload benefit. Because each route remains a separate Cake IR program, route-level analyses and benchmarks remain possible.

Scope, Limitations, and Theoretical Implications

CAKE’s main theoretical implication is that compiler feedback should be treated as an evolvable interface rather than a fixed execution oracle. In standard program synthesis, the representation and verifier are usually designed before search begins. CAKE instead proposes an iterative relationship in which search failures reveal inadequacies in the representation and analysis substrate. This places the work near broader efforts on agentic system evolution, but its object of evolution is narrower and technically concrete: the compiler harness, not the foundation model or general-purpose agent.

The approach also challenges a common abstraction hierarchy in GPU programming. The paper argues that a useful agent-facing language should expose the physical schedule while hiding mechanical bookkeeping. This is neither conventional high-level tiling nor raw assembly generation. Its viability depends on maintaining a sufficiently expressive vocabulary, sound-enough legality checks, stable diagnostics, and deterministic lowering across rapidly changing GPU architectures.

Several limitations remain material. Static analysis is explicitly incomplete and does not establish global GPU correctness or capture all microarchitectural behavior. GPU execution remains the final authority. Performance evidence is concentrated on B200, with cost-model calibration available for B200 and H100 but not uniformly across all supported targets. Non-NVIDIA portability is unmeasured and would require new lowering paths, legality rules, resource models, and calibration data. Compiler evolution remains human-gated, so the system is not fully autonomous in the strongest sense.

The evaluation also leaves open questions about attribution. CAKE combines a representation, a verifier, a cost model, compiler lowering, an evolution policy, and a large validated corpus. Ablations isolating these components would clarify whether the primary benefit arises from typed schedules, localized feedback, compiler evolution, persistent corpus knowledge, or their interaction. Additional comparisons against Triton, CuTe DSL, Gluon, TileLang, and specialized search systems under identical reference-access policies would strengthen the empirical claims.

Practical Consequences and Future Directions

Practically, CAKE suggests a deployment model in which kernel libraries maintain not only optimized binaries and source implementations but also structured schedules, verifier rules, calibration artifacts, and route-level evidence. Such an ecosystem could reduce the cost of retargeting production kernels across GPU generations, particularly when new instruction forms or memory resources invalidate existing lowering strategies.

Future systems could extend the framework in several directions. A first priority is cross-architecture compiler evolution, including AMD and other accelerator backends, while preserving a hardware-explicit scheduling model. A second is stronger formalization of synchronization and memory contracts, potentially integrating agentic CUDA verification systems with Cake IR. A third is adaptive cost modeling that combines static schedule features, CUPTI data, microarchitectural counters, and uncertainty estimates. A fourth is portfolio-level optimization in which dispatch cost, binary size, compilation time, and maintenance burden enter the objective explicitly.

The most consequential development would be a multi-level compiler-agent loop: agents could evolve kernel schedules, compiler analyses, cost models, and workload contracts under separate validation gates. Such a system would require rigorous provenance, regression containment, adversarial testing, and controls against compiler changes that improve benchmark scores by narrowing semantics or exploiting evaluation artifacts.

Conclusion

CAKE presents compiler–agent co-design as an alternative to optimizing kernels against a fixed, opaque compiler environment. Its typed Cake IR exposes warp roles, pipelines, synchronization, and memory placement while delegating mechanical lowering details to the compiler. Its harness converts localized safety, conformance, correctness, and performance evidence into both candidate-level feedback and persistent compiler improvements.

The reported results are substantial: $K=1024$6 median attainment over a tuned FlashML baseline in matched clean-start Flash-KMeans runs, $K=1024$7 geometric-mean improvement over official FlashKDA, up to $K=1024$8 API-level Alpha-MoE speedup, ten of eleven known-kernel comparisons at or above reference performance, and dispatcher-backed gains of $K=1024$9–$D=128$0 across hundreds of shapes. The broader contribution is methodological: effective kernel agents may require not only better search policies or larger models, but also compiler environments capable of learning from the failures generated by search.