Weave: Verified Netlist-to-Schematic Conversion via Layered Graph Layout

Abstract: Converting a SPICE netlist into a human-readable schematic is a longstanding problem in electronic design automation: simulators and machine-learning pipelines readily produce netlists, but designers reason about circuits through diagrams. Recent learning-based approaches translate netlists into schematics probabilistically, yet they provide no guarantee that the generated drawing preserves the original connectivity, and their accuracy degrades sharply as circuits grow. We present Weave, a deterministic converter that turns a SPICE netlist into an LTspice .asc schematic using a layered (Sugiyama-style) graph layout, and that certifies every output by a round-trip connectivity check: the generated schematic is re-parsed into a netlist and compared, net for net, against the input. A result is reported as correct only when the two partitions are identical, giving a binary correctness certificate rather than a similarity score. Weave runs entirely client-side as a single dependency-free file and embeds a pin table for 5093 LTspice symbols. On the identical public Circuits-LTSpice test set used by the state-of-the-art LLM converter Schemato (117 circuits, netlisted with LTspice itself), Weave achieves 100% compilation and 100% round-trip-verified connectivity equivalence, compared with Schemato's reported 76% compilation and a graph-edit-distance similarity of 0.35; notably, 73% of that set exceeds the five-component threshold beyond which Schemato reports losing connectivity accuracy. On a larger and harder corpus, the 3460 netlistable circuits of the official Analog Devices LTspice demo collection, Weave verifies exact connectivity for 88.4% of circuits, with the remaining failures concentrated in a single, well-characterized class of dense multi-pin power modules.

• The paper introduces Weave, a deterministic netlist-to-schematic converter that ensures 100% connectivity preservation through round-trip equivalence testing.
• It employs a Sugiyama-style layered layout with an embedded symbol table to accurately render complex circuit structures and maintain robust net classifications.
• Benchmark results show Weave achieving full compilation success and verified connectivity even in large circuits, outperforming probabilistic methods like Schemato.

Authoritative Summary of "Weave: Verified Netlist-to-Schematic Conversion via Layered Graph Layout"

Motivation and Context

The conversion of SPICE netlists to human-interpretable schematics forms a bottleneck in electronic design automation, especially in workflows integrating simulator or ML-generated netlists. Traditional approaches, including both heuristic algorithms and probabilistic learning-based methods, prioritize aesthetic quality or similarity metrics but lack robust guarantees regarding preservation of connectivity. The absence of such guarantees is problematic for engineering workflows where correctness is paramount. Recent learning-based converters, such as Schemato, display explicit degradation on larger circuits and offer only similarity scores, with compilation rates far below 100%. The paper introduces Weave, a deterministic, verification-first converter employing layered graph layout and certified connectivity preservation via round-trip equivalence testing.

Methodological Framework

Weave parses a SPICE netlist and deterministically generates an LTspice .asc schematic using a Sugiyama-style layered layout (elkjs engine), supplemented by structured placement patterns for special circuit features (feedback loops, divider legs, shunts). The pipeline encompasses:

• Parsing & Net Classification: Comprehensive coverage of SPICE elements, with net classification segregating ground, rail, and signal nets.
• Layered Layout: Signal topology rendered via elkjs, with explicit orthogonal routing and grid alignment for LTspice compatibility.
• Placement Patterns: Out-of-graph handling for nontrivial structures; every wire is net-tagged for certification.
• Symbol Table & Fallback: Embedded pin table for 5093 symbols, with generic fallback blocks ensuring connectivity accuracy for unknown or mismatched parts.
• Round-trip Verification: The .asc output is parsed back, its connectivity partition compared bitwise to the original netlist. Certificates are binary: only exact matches are accepted.
• Safe-mode Ladder: Progressive fallback to simpler layouts if verification fails, ensuring robustness without sacrificing correctness.

The workflow is depicted succinctly in (Figure 1):

Figure 1: Transformer circuit: input netlist (a) and Weave output (b) demonstrating deterministic layout and connectivity preservation.

Weave’s deterministic structure explicitly avoids reliance on training datasets or probabilistic sampling, circumventing issues of data scarcity and unfamiliar symbol placement that plague learning-based alternatives.

Empirical Results and Comparative Evaluation

Benchmarking Against Schemato

On the Circuits-LTSpice benchmark (117 circuits, identical test protocol as Schemato), Weave achieves 100% compilation success and 100% round-trip connectivity equivalence—far superior to Schemato’s 76% compilation and 0.35 GED similarity, with the majority of circuits exceeding component-count thresholds where Schemato loses accuracy. Schematics generated for prototypical circuits such as the transformer circuit and RC band-pass filter are shown in (Figure 1) and (Figure 2):

Figure 2: RC band-pass filter: input netlist (a) and Weave output (b), exhibiting verified connectivity and clean signal flow.

For larger and denser circuits (mean: 14.4 elements; max: 138), Weave verified exact connectivity for 88.4% of 3460 circuits from the Analog Devices LTspice demo corpus, with remaining failures centralized in dense multi-pin power modules. Failure modes are sharply characterized and non-random, arising primarily from absent symbols or unmatched pin counts.

Large-scale verification includes the schematic output for a 32-component RLC step-response network (Figures 5):

Figure 3: Weave output for a 32-component RLC step-response network with verified connectivity for all elements.

The round-trip verifier’s rigor was validated experimentally; deliberately corrupting schematic or netlist input resulted in mismatch reports, demonstrating non-trivial verification and absence of false positives.

Structural Implications

Learning-based methods are fundamentally constrained by probabilistic modeling and training set coverage, especially for large or uncommon topologies. Weave’s deterministic approach and embedded symbol table provide robust placement independent of corpus frequency, with guaranteed connectivity even for unknown symbols. The trade-off is clear: deterministic exactness in connectivity, at the cost of tuneable aesthetic metrics and visual similarity—a direction the authors acknowledge and scope honestly.

Practical and Theoretical Implications

Practical Utility

Weave’s deterministic, fully client-side design (dependency-free, browser-based, batch CLI support) offers accessible, reproducible conversions with robust correctness guarantees. Engineers can integrate Weave seamlessly into simulation workflows, confident of schematic accuracy and reliability, rather than relying on subjective similarity or compilation rates.

Scalability and Extensibility

The safe-mode ladder and placement patterns provide effective hierarchical pruning, as advocated in prior ASG reviews. Limitations observed for dense multi-pin modules and stretched cascades suggest future development of box-contract layouts and hierarchical block-slot optimization, aligning with scalable circuit generation strategies outlined in contemporary literature.

Theoretical Directions

The round-trip binary certificate sets a new standard for netlist-to-schematic conversion correctness, moving beyond average-case similarity metrics. This offers a strong primitive for subsequent aesthetic optimization—building on certified correctness rather than pursuing aesthetic quality absent connectivity guarantees. Future work may extend this paradigm to hierarchical circuit domains, partitioned block layouts, and deeper integration of visual metrics.

Conclusion

Weave introduces a deterministic, verification-first netlist-to-schematic converter achieving exact connectivity preservation on large and diverse circuit benchmarks, decisively outperforming probabilistic state-of-the-art LLM-based converters in both compilation rate and connectivity equivalence. Limitations are well-characterized and form the basis for future work in hierarchical layout and visual optimization. Verified connectivity by construction offers a robust foundation for scalable, aesthetic schematic generation, with broad implications for the future of electronic design automation and ML-driven circuit synthesis.