Lattice patch structure for fixed-frequency transmon quantum computer with high-fidelity CNOT gates

Abstract: Superconducting transmon processors represent a leading platform for large-scale quantum computing due to their high gate fidelities and scalability. However, conventional qubit-coupler-qubit (QCQ) architectures face critical physical and structural bottlenecks, notably frequency crowding [spectator qubit collisions] during system scaling and inefficient mapping onto the standard surface code.To overcome these limitations, we propose a novel lattice-patch architecture that couples four fixed-frequency transmons to a single fixed-frequency coupler.This design enhances qubit connectivity and maps directly onto the surface-code lattice unit [plaquette], thereby minimizing the compilation overhead associated with logical qubit implementation. Furthermore, utilizing an entirely fixed-frequency design intrinsically eliminates susceptibility to external flux noise, ensuring robust operational stability.Multi-level numerical simulations demonstrate CNOT gate fidelities exceeding 0.98 across all six connectivity directions within the patch. Nevertheless, the complex interaction network of the four-qubit architecture induces unintended residual phase accumulation during cross-resonance driving. This parasitic effect necessitates precise calibration, achievable via virtual $R_z$ gates [software phase updates]. Ultimately, our results establish the lattice-patch architecture as an efficient, robust building block for future fault-tolerant quantum computers.

• The paper introduces a novel lattice-patch design that couples four fixed-frequency transmon qubits via a single coupler, achieving CNOT fidelities exceeding 0.98.
• It employs cross-resonance and DRAG pulse sequences optimized through simulation to manage leakage (<2.5%) and crosstalk, ensuring robust bidirectional CNOT operations.
• The architecture enables direct surface-code mapping, reducing hardware overhead and control complexity compared to grid and heavy-hex designs for fault-tolerant quantum computing.

Lattice Patch Structure for Fixed-Frequency Transmon Quantum Computing: Architectural, Operational, and Numerical Analysis

Introduction

This work introduces a new architectural paradigm for superconducting quantum computation, leveraging a lattice-patch topology that couples four fixed-frequency transmon qubits to a single fixed-frequency coupler. The design fundamentally addresses persistent bottlenecks in prevailing architectures—particularly frequency crowding, inefficient surface code mapping, excessive coupler density, and flux noise susceptibility. It directly aligns with the physical requirements for scalable quantum error correction (QEC) schemes utilizing surface codes, which remain the dominant pathway for achieving fault-tolerant quantum computation with superconducting qubits.

Comparative Architectural Analysis

The two leading architectures in contemporary superconducting platforms are Google’s grid and IBM’s heavy-hexagon. The grid provides high connectivity and surface code mapping at the expense of escalating coupler complexity and parasitic interactions, while the heavy-hex structure reduces such interactions but incurs significant gate compilation overhead due to lower connectivity and inefficient surface code mapping.

In contrast, the lattice-patch design couples four fixed-frequency qubits through a single fixed-frequency mediator, providing high connectivity with minimized hardware overhead. Critically, the structure maps directly onto the surface-code plaquette, enabling efficient logical qubit encoding with reduced compilation and control-line complexity.

Figure 1: Comparative illustration of Google grid, IBM heavy-hexagon, and the lattice-patch architecture, highlighting connectivity, coupler density, and surface-code mapping efficiency.

Physical Model and System Hamiltonian

The lattice-patch is architected with four transmon qubits capacitively coupled to an LC resonator acting as the central mediator. Operating in the fixed-frequency regime ensures suppression of $1/f$ flux noise, a crucial source of decoherence. Detunings are engineered to be several hundred MHz, while the central coupler sits $\sim$2 GHz above the qubit band, enforcing dispersive interaction and mitigating energy exchange.

The Hamiltonian incorporates multi-level transmon dynamics to explicitly capture leakage phenomena, with the total system treated as the tensor product of qubit and resonator Fock states, ensuring both physical accuracy and computational tractability.

Figure 2: Circuit schematic and lumped-element model of the lattice-patch system, emphasizing qubit-coupler connectivity and scalable lattice tiling for surface-code mapping.

Pulse Design and Quantum Gate Optimization

Control of two-qubit operations employs cross-resonance (CR) pulse sequences, augmented by DRAG-based Gaussian envelopes to suppress leakage and crosstalk. A grid-based parameter sweep coupled with Nelder-Mead simplex optimization determines the optimal pulse configuration for both forward (control-to-target) and reverse (target-to-control) CNOT operations. Calibration via virtual $R_z$ gates rectifies residual phase errors arising from unintended interactions, which is critical given the increased qubit density.

Pulse protocols preserve operational simplicity by leveraging universal sequences and reduce hardware complexity by avoiding tunable coupler and flux-bias lines, while enabling robust bidirectional gate fidelity.

Figure 3: Pulse waveforms illustrating CR drive and DRAG protocols for forward and reverse CNOT gate implementation, indicating the temporal and frequency domain structure.

Numerical Results and Error Analysis

Extensive simulation of the lattice-patch system demonstrated CNOT gate fidelities exceeding 0.98 for most connectivity directions. Residual $ZZ$ interactions and leakage errors were quantitatively assessed: average leakage out of the computational basis remained less than $2.5\%$, confirming the efficacy of energy detunings and DRAG corrections. Notably, gate performance was consistent across varying coupler strengths and qubit frequencies, attesting to architectural robustness.

Bidirectional CNOT gates were realized without physical overhead via additional Gaussian pulses and virtual gates, confirming operational flexibility. Effective fidelities for reverse-direction gates, considering Hadamard pulse errors, further highlighted the importance of system-level error budgeting.

Strong numerical results from this architecture include:

• Forward CNOT average fidelities: $>$0.98 (six directions);
• Reverse CNOT effective fidelities (including Hadamard pulses): 0.90–0.98;
• Leakage errors: $<$0.025 per gate;
• Maximum success probabilities: $>$0.99 in several gate channels.

Scalability, Structural Advantages, and Practical Implications

Periodic tiling of the lattice-patch units forms a global square lattice congruent with surface-code requirements. This eliminates the exponential growth in coupler count inherent to grid architectures and obviates the need for SWAP gate overhead and complex compilation seen in heavy-hex layouts. Single-qubit gate fidelities remain high ($\sim$0.99), preserving error correction thresholds.

The practical implications are profound: the architecture serves as a fault-tolerant building block, directly enabling large-scale quantum surface code implementations with minimal physical overhead and enhanced operational stability—particularly under fixed-frequency constraints.

Theoretical and Engineering Prospects

The numerical results validate the foundational viability of the lattice-patch structure for scalable QEC systems. This topology offers distinct advantages in terms of hardware simplicity, control-line density, and robustness against flux noise. However, frequency crowding and residual interactions persist as limiting factors in certain gate channels, necessitating advanced frequency allocation schemes and pulse optimization in physical implementations.

Future developments may include:

• Integration of tunable couplers to further shorten gate durations and enhance noise resilience;
• Application of echoed CR and active-cancellation gate protocols for improved fidelity;
• Explicit open-system modeling incorporating Lindblad dynamics for environmental noise;
• Hardware-level optimization of frequency detuning and coupling strengths for uniform gate performance.

Conclusion

The lattice-patch architecture for fixed-frequency transmon quantum processors represents a significant advancement in hardware design for scalable quantum computation, aligning directly with surface code QEC requirements. The demonstrated high-fidelity CNOT gates, architectural scalability, and minimized control complexity establish this topology as a credible candidate for next-generation superconducting quantum processors. Ongoing research should focus on further optimization, practical realization, and integration with advanced control protocols to fully exploit the theoretical and engineering potential of this design.