System-Level Design of Scalable Fluxonium Quantum Processors with Double-Transmon Couplers

Abstract: Fluxonium qubits combine long coherence times with strong anharmonicity, making them a promising platform for scalable superconducting quantum processors. Recent experiments have demonstrated high-fidelity operations in multi-qubit processors while suppressing stray qubit interactions using fluxonium-transmon-fluxonium (FTF) architectures. However, scaling such systems to larger arrays is constrained by a trade-off between achievable coupling strength, crosstalk suppression and qubit-qubit spacing required for wiring in a two-dimensional architecture. Multimode couplers, such as the double-transmon coupler (DTC), provide a promising pathway to overcome this limitation by enabling stronger interactions without compromising qubit spacing and isolation. Here, we develop a quantitative design framework for fluxonium-based quantum processors employing DTCs. Central to this work is a frequency-partitioned architecture that places qubit transitions, tunable-coupler excitations, and resonator modes in well-separated spectral regions. This structured allocation reduces parameter interdependence and enables the concurrent optimization of gate operations, readout, and qubit reset. By formulating device design as a multi-objective optimization problem under realistic experimental constraints and fabrication-induced disorder, we develop a tractable sequential workflow and determine a feasible parameter regime that simultaneously supports high-fidelity single- and two-qubit gates, fast qubit reset, and robust dispersive readout. These results establish a system-level architectural methodology that links circuit parameters to processor-level performance, and provide an experimentally actionable pathway toward scalable fluxonium quantum processors.

• The paper presents a novel quantum architecture that employs fluxonium qubits and double-transmon couplers to suppress crosstalk and leakage.
• It uses a hierarchical multi-objective optimization approach that maps circuit parameters to benchmarks like >99% single-qubit fidelity and low two-qubit leakage.
• The design strategically allocates frequency bands to ensure robust operation under realistic fabrication disorder and enable parallel gate operations.

Scalable Fluxonium Quantum Processors Enabled by Double-Transmon Couplers

Architectural Motivation and System-Level Paradigm

The paper "System-Level Design of Scalable Fluxonium Quantum Processors with Double-Transmon Couplers" (2604.26373) presents a rigorous system-level architecture for superconducting quantum computation, based on fluxonium qubits interconnected via double-transmon couplers (DTCs). The approach is motivated by the unique combination of long coherence times and strong anharmonicity of fluxonium qubits, essential for minimizing detrimental cross-coupling and crosstalk in large-scale quantum systems. By integrating DTCs, which offer multimodal coupling and tunable interaction strengths, the architecture overcomes critical bottlenecks inherent in both direct capacitive/inductive and single-mode coupler paradigms regarding qubit isolation, scalable connectivity, and interaction on/off ratio.

Figure 1: Large-scale grid of fluxonium qubits (red) interconnected by blue double-transmon couplers (DTC); right: detailed coupling circuit.

The architectural requirements addressed include: suppression of microwave-driven crosstalk during parallel gates, minimization of flux-bias crosstalk, elimination of spectator-induced crosstalk, and scalable spatial arrangement for wiring. The DTC mechanism leverages flux-tunable cancellation of inductive pathways, achieving nearly perfect isolation at the "turn-off" flux and robust coupling at the "turn-on" flux, as depicted in the circuit schematic above.

Hamiltonian Construction and Multi-Objective Optimization Methodology

The device Hamiltonian encompasses fluxonium qubits, DTCs, readout/reset resonators, and external drives, formulated from constituent energies ($E_{C}$, $E_{J}$, $E_{L}$) and coupling strengths. A sophisticated inverse design framework links circuit parameters to processor-level DiVincenzo-style benchmarks: single- and two-qubit fidelities, gate leakage, spectator crosstalk, dispersive readout metrics, active reset performance, and disorder robustness.

Figure 2: Multi-objective optimization workflow mapping input parameters $\mathbf{x}$ to Pareto optimal solutions by sequential evaluation of physical metrics and robustness.

Given the high-dimensional, nontrivial interplay of parameters, the optimization is structured hierarchically: frequency allocation precedes local qubit parameter selection, followed by DTC coupling refinement, gate metric evaluation, crosstalk mitigation, and resonator parameter tuning. This sequential decoupling enables tractable convergence to robust operational regimes, rather than brute-force global minimization.

Frequency Allocation, Spectral Isolation, and Robustness

A notable contribution is the frequency-partitioned architecture: qubit computational transitions, coupler modes, and resonator bands are mapped to non-overlapping spectral regions. This approach mitigates frequency collisions and parameter interdependence—crucial for robust calibration and fabrication tolerance in large-scale devices.

Figure 3: Optimized frequency allocation and robustness analysis. Colored bands illustrate separation between qubit, DTC, and resonator transitions under realistic parameter variation (100 samples).

The allocation ensures: reset resonator frequencies below plasmon transitions; DTC "on" modes resonant with plasmon frequencies for gate operation; "off" modes detuned to suppress spectator crosstalk; and readout resonators placed above all fluxonium transitions to guarantee dispersive measurement. Robustness analysis affirms that these spectral gaps persist under stochastic $2$-$5\%$ fabrication disorder, preventing spurious resonances and preserving operational integrity.

Single- and Two-Qubit Gate Performance: Leakage and Fidelity

The design achieves single-qubit gate fidelities exceeding $99.99\%$ for gate times $t_g=50$ ns, via judicious selection of $E_{J}$ and $E_{L}$. For two-qubit MAP gates, the leakage probability is strictly bounded ($E_{J}$0) only if the fluxonium-DTC coupling is engineered to $E_{J}$1 MHz.

Figure 4: Statistical robustness of MAP gate leakage probability $E_{J}$2 vs. coupling strength, demonstrating $E_{J}$3 compliance with threshold for $E_{J}$4 MHz.

Figure 5: MAP gate infidelity breakdown as a function of DTC flux bias, showing decoherence rates and leakage for multiple transitions. Dominant source is energy relaxation, with dephasing and leakage subdominant.

Gate infidelities are primarily dictated by dielectric loss and flux noise on plasmon transitions; dephasing is suppressed near DTC sweet spots due to first-order flux insensitivity. The architecture achieves two-qubit MAP fidelities exceeding $E_{J}$5 across relevant transition manifolds.

Spectator Crosstalk and Parallel Gate Isolation

A central architectural claim is suppression of spectator-induced crosstalk ($E_{J}$6) during simultaneous gate execution. Robustness analysis shows that the optimized detuning ($E_{J}$7 GHz) between DTC "off" modes and plasmon transitions maintains $E_{J}$8 kHz over all disorder samples.

Figure 6: Spectator-induced crosstalk $E_{J}$9 (frequency shift) is strictly bounded below $E_{L}$0 kHz for all tested transitions under $E_{L}$1 fabrication disorder.

The analysis further demonstrates that reducing detuning to $E_{L}$2 GHz increases crosstalk by an order of magnitude, validating the necessity of strategic spectral partitioning.

Figure 7: Frequency allocation (left) and robustness of crosstalk (right) for alternative DTC parameters. Insufficient detuning yields weaker crosstalk suppression under disorder.

Figure 8: Crosstalk-induced MAP gate infidelity $E_{L}$3 vs. crosstalk strength $E_{L}$4. Fidelity loss remains below $E_{L}$5 for $E_{L}$6 kHz, confirming scalability of parallel gates.

Reset and Dispersive Readout Optimization

The architecture integrates low-frequency resonators for active reset, maintaining $E_{L}$7 in $E_{L}$8 ns for optimal $E_{L}$9 and $\mathbf{x}$0. Readout resonators are engineered for dispersive shift $\mathbf{x}$1 MHz and critical photon number $\mathbf{x}$2, with SNR optimized via $\mathbf{x}$3 for quantum-nondemolition measurement.

Figure 9: Readout performance: (a) dispersive shift, (b) critical photon number, (c) SNR, as a function of resonator frequency and coupling; optimal readout point marked (yellow dot).

Proactive avoidance of Purcell relaxation and photon shot-noise on gate states is ensured by strategic frequency separation.

Double-Transmon Coupler Physics and Parametric Tunability

The DTC spectral structure is analyzed in detail: common and differential modes are flux-tunable, with mode degeneracy at "turn-off" flux yielding vanishing effective coupling. Capacitive loading and junction asymmetry are shown to be tolerable up to $\mathbf{x}$4, ensuring scalability for 2D architectures.

Figure 10: DTC normal mode frequencies vs. external flux bias, demonstrating tunable mode structure for coupling control.

Figure 11 further illustrates the transition frequencies and drive strengths for all MAP gate channels, establishing the parameter selection strategy for low-leakage operation.

Figure 11: (a) MAP transition frequencies; (b) drive strengths for eight MAP transitions, enabling informed selection of optimal gate channel.

Practical Implications and Theoretical Outlook

The system-level design methodology provides a robust, quantitative link between circuit-level physical parameters and processor-level benchmarks. The DTC-based fluxonium architecture achieves strong, tunable interaction without excessive wiring density, preserves quantum state isolation, and enables parallel, high-fidelity gate operations—critical for scaling toward fault-tolerant computation.

Theoretical implications extend to automated, model-driven quantum processor design, where spectral partitioning decouples parameter optimization across subsystems, mitigating calibration overhead and fabrication disorder. Practically, the architectural framework is applicable to other coupler paradigms, including tunable transmon and resonator-based schemes, contingent on analogous benchmarking metrics.

Conclusion

The paper presents a comprehensive architectural framework for scalable superconducting quantum processors centered around fluxonium qubits and double-transmon couplers. The core contributions include frequency isolation of operational channels, systematic multi-objective parameter optimization, robust suppression of leakage and crosstalk, and enhanced disorder tolerance. The proposed methodology advances the practical realization of large-scale, high-fidelity, low-overhead quantum processors, and establishes a foundation for automated system-level design in quantum hardware (2604.26373).