- The paper demonstrates that open-source EDA flows and PDKs can produce manufacturable ASIC designs with performance metrics comparable to commercial-grade chips, as evidenced by the baseline chip achieving 82MHz and 52.3mW power consumption.
- The paper details a modular RISC-V SoC architecture that supports custom ISA extensions, accelerators, and experimental cores, facilitating domain-specific customization.
- The study highlights a successful educational implementation at ETH Zurich, where 65 students engaged in ASIC projects, resulting in multiple tapeout-qualifying and manufacturable designs.
Motivation and Context
Recent upsurges in demand for domain-specific architectures (DSAs), especially for AI, robotics, and automotive applications, have underscored critical shortages in VLSI engineering talent. Legacy VLSI curricula tend to rely on NDA-restricted PDKs and commercial EDA tools, impeding access for many institutions and precluding true hands-on ASIC education. Advances in open-source EDA toolchains, hardware platforms, and open PDKs create the possibility for broadly accessible and scalable silicon design training, addressing structural bottlenecks in industry and academia.
System Architecture
Croc is a microcontroller-grade, modular RISC-V SoC platform explicitly engineered to facilitate extensible domain-specific customization. Its architecture bifurcates into two primary domains:
- Croc domain: Incorporates a production-grade CVE2 RISC-V core, basic peripherals, and a tightly coupled crossbar interconnect. The infrastructure supports ISA extensions and custom interconnect modifications.
- User domain: Exposes OBI crossbar ports and custom interrupts, allowing integration of accelerators, co-processors, specialized peripherals, and experimental RISC-V cores.
The complete RTL, software setup, and documentation are centrally available. Croc targets the IHP 130nm open PDK, leveraging Yosys for synthesis, OpenRoad for physical design, and Verilator for simulation. Containerized OS EDA tools (IIC-OSIC-TOOLS) facilitate reproducible flows. FPGA emulation is supported via Digilent Genesys 2 and nextpnr, streamlining pre-silicon bringup.
Pedagogical Implementation and Numerical Outcomes
The inaugural iteration of ETH Zurich’s restructured VLSI course, anchored on Croc, engaged 65 students across 33 ASIC projects. Of these, 30 projects yielded manufacturable layouts, with 18 qualifying as tapeout candidates. Fiscally constrained, five designs were selected for fabrication—spanning serial communication peripherals, DMA, and a crypto accelerator. Notably, the baseline chip demonstrator (MLEM) achieved 82MHz operational frequency and 52.3mW power consumption at 1.2V, on par with commercial/research SoCs of similar complexity in mature technology nodes (2606.25673). The course demonstrated a scalable model for hands-on silicon education, evidencing viability of open-source tools and PDKs for robust ASIC implementation.
Contrasts, Claims, and Implications
The paper establishes the claim that open-source flows and open PDKs enable educational ASIC projects with silicon metrics matching commercial-grade chips—contradicting entrenched assumptions regarding the necessity of closed-source EDA and proprietary PDKs for industry-relevant outcomes. Croc’s extensible architecture permits fine-grained SoC customization, supporting accelerators and ISA extensions, thus aligning pedagogical outcomes with practical DSA design needs.
The course’s transferability and scalability are substantiated by its reliance on freely accessible tooling and openly licensed teaching materials. Furthermore, the silicon results underscore that open-source methodologies can deliver manufacturable, industry-grade chips even at the undergraduate and graduate education level, thus broadening access beyond elite institutions.
Theoretical and Practical Implications
Practically, Croc presents a replicable blueprint for democratized ASIC education, lowering barriers related to licensing, security, and infrastructure. Theoretically, the work evidences that open-source ecosystems can close the gap between academic training and industry practice, catalyzing a broader and more diverse pipeline of next-generation chip designers. Future developments may leverage more advanced open PDKs, integrate differentiated accelerator designs, or expand flows to sub-100nm technology nodes as open-source processes mature.
Future Directions
Anticipated future work includes scaling the curriculum across institutions, further refining the Croc platform for deeper domain-specificity, and extending the open-source flow to more advanced process nodes. Integrating formal verification, power-aware synthesis, and hardware security primitives via open tools could substantially enrich pedagogical and research outcomes. Cross-institutional collaborations leveraging Croc may foster standardized, widely accessible silicon-centric education frameworks.
Conclusion
The Croc platform demonstrates that open-source SoC templates, EDA flows, and PDKs are sufficient for training competent ASIC designers and for producing manufacturable silicon indistinguishable from conventional closed-source flows in mature nodes. This approach offers a scalable, transferable, and reproducible paradigm for hands-on VLSI education aligned with current and future industry needs. The implications extend to both university curricula and professional upskilling in semiconductor engineering.
