Surface-Code Thresholds and Qubit Footprints in Shuttling-Based Spin-Qubit Railways

Abstract: We present a fault-tolerant mapping of rotated surface codes onto a $2\times N$ silicon spin-qubit railway architecture, utilizing electron shuttling to resolve the wiring fan-out bottleneck. Employing circuit-level noise modeling, we evaluate threshold performances across various noise biases. We demonstrate that shuttling check qubits instead of data qubits fundamentally improves system thresholds. Crucially, under a noise model biased towards dephasing for spin-qubit shuttling, the non-CSS XZZX surface code outperforms standard CSS variants. By tailoring the topological code to this specific inherent bias, we show that the Megaquop footprint is achievable with a distance 7 code requiring a $p = 10^{-3}$ physical error rate, highlighting a pathway for substantial hardware reductions in early fault-tolerant quantum processors.

• The paper demonstrates that check-shuttling protocols yield significant threshold improvements, achieving up to 4.0×10⁻³ under high Z-bias conditions.
• It leverages rotated surface codes, notably the XZZX variant, combined with a hardware-informed noise model to exploit asymmetric dephasing errors.
• The optimized 2×N railway architecture reduces the qubit footprint by up to 72%, enabling practical fault-tolerant quantum computation at moderate error rates.

Surface-Code Thresholds and Qubit Footprints in Shuttling-Based Spin-Qubit Railways

Architectural Motivation and Surface Code Adaptation

This work presents an in-depth analysis of surface-code quantum error correction adapted to a shuttling-based bilinear silicon spin-qubit "railway" architecture, focusing on both hardware-driven noise asymmetry and connectivity constraints intrinsic to next-generation quantum dots. Standard 2D surface-code layouts are challenging in dense silicon platforms due to severe wiring fan-out and control access bottlenecks. The adoption of a 2xN "railway" geometry, where electron shuttling is leveraged to dynamically realize connectivity, addresses these system-level barriers while still supporting topological error correction.

The principal innovation is the mapping of rotated surface codes (RSCs)—including both the standard CSS variant and the non-CSS XZZX variant—onto this architecture, with syndrome extraction realized by coherent electron shuttling along parallel rails and transversal entangling gates between rails. The mapping systematically separates data qubits and check (ancilla) qubits onto parallel tracks, with architectures designed for either data-shuttling or, preferably, check-shuttling syndrome extraction protocols.

Circuit-Level Noise Model for Shuttling and Asymmetric Error Channels

A rigorous, hardware-informed circuit-level noise model is developed, explicitly capturing the impact of shuttling dynamics in the presence of micromagnet gradients and spin-orbit coupling (SOC)—both dominant in silicon spin qubit arrays. Stochastic trajectory deviations and magnetic field gradients are shown to convert into strongly biased Pauli error channels. The effective error bias can be systematically engineered via confining potential geometry and shuttling directionality relative to the quantization axis. Crucially, the noise model admits pronounced Z-bias (dephasing) during shuttling, reflecting realistic experimental constraints.

This bias enables tailored code selection: under high dephasing environments, the XZZX surface code, which can exploit asymmetric error channels, outperforms conventional CSS codes. Analytical derivations and numerical simulations specify the resulting single-qubit noise channels and their dependence on control and transport protocols.

Optimized Shuttling Protocol: Train Schedule and Syndrome Extraction

The paper introduces the "Train Schedule" shuttling protocol, an optimized scheme for syndrome extraction with strict commutation and minimum hook error proliferation. The check-shuttling variant (moving ancillas rather than data) consistently yields higher thresholds since stationary data qubits, idled with Z-bias, minimize the propagation of correlated (hook) errors and preserve noise asymmetry favorable for the XZZX code. The protocol is generalized for arbitrary code distance, employing a "snake order" for qubit placement to satisfy syndrome extraction constraints with minimal idle time and shuttling overhead.

Numerical Thresholds and Hardware Footprint Implications

The principal numerical results indicate notable threshold improvements and substantial reductions in the qubit footprint required for fault-tolerant logical operation:

• Under symmetric (depolarizing) noise, CSS codes achieve threshold physical gate error rates of roughly $2.2 \times 10^{-3}$, rising to $2.65 \times 10^{-3}$ for check-shuttling.
• With pronounced Z-bias (e.g., noise bias $n=100$), the XZZX code in check-shuttling mode achieves a threshold up to $4.0 \times 10^{-3}$, clearly surpassing the CSS variant.
• The minimum qubit footprint necessary for reaching the "Megaquop" logical error regime is reduced by 64–72% under strong bias, requiring, for example, only 97 physical qubits for a distance 7 code at $p=0.001$.
• For both physical error rates ($p=0.001$ and $p=0.003$), the required code distance and total footprint for practical logical error suppression are minimized when maximizing both idling and shuttling Z-bias.

These results highlight the benefit of co-designing the error-correcting code and the hardware noise profile. In particular, the intrinsic bias of spin-qubit-based shuttling architectures aligns naturally with the XZZX code’s asymmetric error suppression capabilities.

Theoretical and Practical Implications

The paper's conclusions have several key implications:

• Architectural Co-design: Optimal performance in constrained geometries like 2xN railways necessitates not just hardware-aware codes, but also motion and syndrome extraction protocols that preserve favorable noise characteristics. Shuttling check qubits (rather than data) consistently enhances thresholds and leverages idling bias.
• Bias Utilization Strategy: Surface codes that exploit physical noise bias, particularly non-CSS variants like XZZX, can yield high thresholds and dramatic hardware savings, provided gate implementations preserve bias (as in CZ-based architectures).
• Scalability and Feasibility: Moderate code distances and physical footprints sufficient for practical fault-tolerant quantum computation (e.g., Megaquop regime) are now within reach for silicon spin-qubit platforms, especially as multi-rail shuttling geometries integrate further with industrial CMOS processes.
• Extensions and Future Work: The generalized shuttling protocol could potentially be adapted to other stabilizer codes or higher-dimensional logical encodings if suitable graph mappings can be found. As physical error rates decrease and control fidelities improve, the approach lays a foundation for scalable, bias-tailored quantum processors.

Conclusion

This study provides a comprehensive analysis of the interplay between surface code structure, syndrome extraction protocols, and hardware noise in shuttling-based spin-qubit railways. By introducing a check-shuttling protocol and exploiting bias-aware non-CSS codes, substantial improvements in both logical error thresholds and physical-qubit resource requirements are demonstrated. The results position the 2xN shuttling railway as a promising template for near-term fault-tolerant quantum computing in semiconductor qubit platforms, provided noise bias and code/architecture alignment are carefully co-optimized.