Distributed Quantum Error Correction with Bivariate Bicycle Codes in a Modular Architecture

Abstract: Quantum low density parity check (qLDPC) codes, particularly bivariate bicycle (BB) codes, achieve competitive fault tolerance thresholds while offering substantially higher encoding rates than planar surface codes. However, their intrinsically long-range stabilizer structure makes them difficult to implement on monolithic devices with nearest neighbor connectivity and limited qubit capacity. In this work, we study the realization of a BB code in a modular multiprocessor architecture, where quantum processors are interconnected through shared Bell pairs. We consider processors with all to all internal connectivity, which is feasible on trapped ion and neutral atom platforms, enabling flexible local gate execution while inter-processor (nonlocal) gates are mediated by shared entanglement. We describe a star network architecture that can realize this distributed setting. We partition the qubits of the [[144,12,12]] BB code across 4, 6, and 12 quantum processors and analyze the resulting logical error rates and pseudo-threshold performance under circuit level noise by varying the number of processors and a scaling factor that captures the additional noise associated with nonlocal operations. We use Monte Carlo simulations with BP+OSD decoding and extend the previously known BB code ansatz to the distributed setting. Our results provide architectural insight and design considerations for distributed BB codes in modular quantum computing architectures.

• The paper presents the implementation of bivariate bicycle (BB) codes in modular quantum architectures to overcome nonlocal stabilizer measurement challenges.
• BB codes use a toroidal lattice and are distributed across quantum processors, facilitating nonlocal gates via entanglement-driven interactions.
• Simulation shows threshold degradation due to partitioning, highlighting the trade-off between scalability and nonlocal noise in modular setups.

Distributed Quantum Error Correction with Bivariate Bicycle Codes in a Modular Architecture

Motivation and Context

Scalable, fault-tolerant quantum computing necessitates architectures that mitigate both circuit-level noise and limitations imposed by hardware connectivity. Quantum low density parity check (qLDPC) codes, particularly bivariate bicycle (BB) codes, present competitive noise thresholds and superior encoding rates relative to planar surface codes, but their implementation is hampered by the requirement for geometrically nonlocal stabilizer measurements. Monolithic platforms with nearest neighbor connectivity are poorly matched to these demands, motivating the realization of BB codes in modular, multiprocessor architectures where quantum processors (QPUs) are interconnected via photonic entanglement resources.

BB Code Construction and Syndrome Extraction

The [[144,12,12]] BB code is constructed on a toroidal lattice with $\ell = 12$, $m = 6$, specified by sparse circulant matrices $A$ and $B$. The stabilizer structure is inherently nonlocal, with syndrome extraction requiring multi-qubit CNOT interactions spanning distant qubits.

Figure 1: Depth-8 syndrome measurement cycle circuit for BB codes, ensuring constant circuit depth independent of lattice size.

The syndrome extraction proceeds in eight time steps with carefully scheduled CNOT rounds to couple each check ancilla with its six neighboring data qubits. This fixed-depth circuit is crucial for robust error correction in modular settings.

Entanglement-Assisted Nonlocal Gate Realization

When partitioned across QPUs, remote CNOT operations are implemented via shared Bell pairs and feedforward-based corrections. Communication qubits from each QPU establish entanglement with the central switch, enabling nonlocal gates despite the absence of direct physical connectivity.

Figure 2: Remote CNOT protocol between QPUs mediated by a shared Bell pair, with classical measurement outcomes dictating necessary Pauli corrections.

The architecture supports all-to-all internal connectivity within QPUs, realized in platforms such as trapped ions and neutral atoms, minimizing intramodule routing overhead.

Modular Star Network Architecture

To distribute the BB code, the lattice columns are partitioned into contiguous blocks assigned to QPUs. The star network architecture features a central quantum switch responsible for entanglement generation and routing.

Figure 3: QPU partitioning of the [[144,12,12]] BB code for $N_{\mathrm{QPU}} = 6$, highlighting local vs. nonlocal interactions for a selected cell.

Figure 4: Star network architecture with six QPUs connected via a quantum switch; communication qubits generate entangled pairs for nonlocal operations through Bell-state measurements.

This architecture enables flexible code partitioning, but the frequency and fidelity of nonlocal gates are contingent upon interconnect quality, directly impacting logical error rates.

Noise Model and Simulation Methodology

A circuit-level stochastic Pauli noise model distinguishes between local ($p$) and nonlocal ($\alpha p$) CNOT gates, where $\alpha \ge 1$ scales the nonlocal gate error rate. This reflects degradation from imperfect entanglement links, Bell-pair swapping, and measurement-based Pauli corrections. BP+OSD decoding is used to extract logical error rates and pseudo-thresholds from Monte Carlo simulations.

Threshold Behavior and Fitting Ansatz

The logical error rate per cycle, $p_L(p,\alpha)$, is modeled with a power law fit structured by BB circuit distance and parametrized corrections dependent quadratically on $\alpha$. This ansatz yields precise characterization and enables extrapolation to lower physical error rates.

Figure 5: BB144 threshold fitting for 12 QPUs with quadratic $m = 6$0 dependence; solid curves represent the fit, dashed lines indicate extrapolation, and asterisks denote pseudo-thresholds.

Increasing $m = 6$1 monotonically reduces the pseudo-threshold, indicating the penalty associated with stronger nonlocal noise.

Figure 6: Quadratic $m = 6$2 dependent threshold fits for 6 QPUs, showing upward shifts in logical error curves and decreasing pseudo-thresholds as $m = 6$3 increases.

Figure 7: Quadratic $m = 6$4 dependent threshold fits for 4 QPUs; reduced partitioning maximizes pseudo-threshold stability under nonlocal gate noise.

Comparative Analysis Across QPU Partitions

Figure 8: Comparison of extracted pseudo-thresholds $m = 6$5 for 4, 6, and 12 QPU partitions as a function of $m = 6$6, illustrating scalability-threshold trade-offs.

For $m = 6$7, pseudo-thresholds are nearly identical across partitions, but higher $m = 6$8 values disproportionately affect configurations with more partitioning (higher $m = 6$9). These findings quantitate the threshold cost incurred by modularity and underscore the importance of minimizing nonlocal gate frequency.

Practical and Theoretical Implications

This research rigorously quantifies the interplay between modular architecture scale and distributed error correction performance in the context of BB codes. The results highlight a clear trade-off: modular partitioning increases scalability and hardware compatibility but incurs logical threshold penalties due to elevated nonlocal noise. Minimizing the number of QPUs or improving interconnect fidelity is critical to maintaining robust error suppression.

The theoretical extension of the BB logical error ansatz to distributed settings enables systematic architectural analysis and informs hardware design choices for future quantum processors. Improved scheduling, optimized qubit placement, and enhanced entanglement distribution strategies could further mitigate nonlocal error cost.

Conclusion

Distributed implementation of the [[144,12,12]] BB code in modular architectures yields practical error suppression closely comparable to monolithic realizations when nonlocal gate noise is kept minimal. However, threshold degradation becomes pronounced for higher degrees of partitioning and unfavorable $A$0 scaling. The quadratic $A$1-dependent ansatz introduced in this work provides a robust framework for extrapolation and architectural optimization. Continued development of quantum interconnects and investigation of correlated nonlocal error mechanisms will be pivotal in advancing modular, fault-tolerant quantum computation.