Towards Ultra-High-Rate Quantum Error Correction with Reconfigurable Atom Arrays

Abstract: Quantum error correction is widely believed to be essential for large-scale quantum computation, but the required qubit overhead remains a central challenge. Quantum low-density parity-check codes can substantially reduce this overhead through high-rate encodings, yet finite-size instances with practical logical error rates often achieve encoding rates only around or below $1/10$. Here, building on a recent ultra-high-rate construction by Kasai, we identify new structural conditions on the underlying affine permutation matrices that make encoding rates exceeding $1/2$ compatible with efficient implementation on reconfigurable neutral atom arrays. These conditions define a co-designed family of ultra-high-rate quantum codes that supports efficient syndrome extraction and atom rearrangement under realistic parallel control constraints. Using a hierarchical decoder with high accuracy and good throughput, we study the performance under a circuit-level noise model with $p=0.1\%$, achieving per-logical-per-round error rates of $1.3_{-0.9}^{+3.0} \times 10^{-13}$ with a $[[2304,1156,\leq 14]]$ code and $2.9_{-1.5}^{+3.1} \times 10^{-11}$ with a $[[1152,580,\leq 12]]$ code. These results approach the teraquop regime, highlighting the promise of this code family for practical ultra-high-rate quantum error correction.

• The paper introduces a new co-designed family of quantum LDPC codes that achieve encoding rates over 1/2 with efficient syndrome extraction on neutral atom arrays.
• It employs affine permutation matrices with commuting constraints to simplify atom rearrangements, reducing syndrome extraction steps to a constant number.
• Numerical results show logical error rates near the teraquop regime, significantly lowering physical qubit overhead compared to traditional surface codes.

Ultra-High-Rate Quantum Error Correction with Reconfigurable Atom Arrays

Introduction and Context

The paper "Towards Ultra-High-Rate Quantum Error Correction with Reconfigurable Atom Arrays" (2604.16209) proposes and systematically explores a new co-designed family of quantum error-correcting codes (QECCs) that achieve ultra-high encoding rates—specifically, rates exceeding 1/2—while supporting efficient syndrome extraction on reconfigurable neutral atom arrays. This represents a significant progression toward quantum LDPC (qLDPC) codes with practical logical error rates at experimentally relevant block sizes, addressing the historically limiting qubit overhead seen in the widespread surface code and existing qLDPC constructions.

Code Construction: Affine Permutations and Hardware Co-Design

The paper builds on the Kasai construction, which introduced CSS-type quantum LDPC codes defined by block-circulant matrices composed from affine permutation matrices (APMs), resulting in codes with rates approaching 1/2 at large blocklengths. Key to this work is the identification and imposition of novel structural constraints on the family of APMs such that the quantum code not only preserves high rate and finite-size distance but is compatible with efficient implementation on hardware that supports reconfigurable parallel and local transport operations (particularly, crossed AOD architectures common in neutral atom platforms).

The central innovation is the commutation-based co-design: By choosing a reference APM $A$ with high-order orbits and constraining all syndrome extraction permutations to commute with $A$, the rearrangement of atoms required for stabilizer measurement can be decomposed into simple cyclic shifts within fixed orbits plus minor inter-orbit permutations. This dramatically reduces the overhead of compiling syndrome extraction schedules into hardware transport primitives (reducing from generic $O(\log P)$ steps to a constant number). The explicit hardware-tailored codes constructed include families such as [1152, 580, ≤12] and [2304, 1156, ≤14], each demonstrating scalable and feasible atom array layouts, with syndrome extraction times estimated in the few-millisecond regime per round on contemporary hardware.

Decoding and Performance: Numerical Results

To address the challenge of simulating and decoding logical errors at extremely low rates ($\lesssim 10^{-11}$ per logical per round), the authors implement a three-tier hierarchical decoder that escalates failed cases through belief propagation (BP), relay BP, and an exact integer-programming (IP) decoder. The architecture is validated for both phenomenological and full circuit-level noise models at $p = 0.1\%$ physical error rate, neglecting idling errors (consistent with the coherence characteristics of neutral atom systems).

Notably, the codes achieve per-logical-qubit, per-round error rates of $2.9_{-1.5}^{+3.1}\times 10^{-11}$ for [1152, 580, ≤12] and $1.3_{-0.9}^{+3.0}\times 10^{-13}$ for [2304, 1156, ≤14], with logical block error rates at or below $10^{-10}$. These codes are thus shown to operate close to the so-called "teraquop regime"—the threshold believed necessary for scalable, utility-scale quantum computation. These results demonstrate a substantial reduction in physical qubit overhead (physical-to-logical ratio ≈ 2 for rates >1/2, compared to ≳100 for surface code), without sacrificing the decoding performance required for fault-tolerance.

Implications and Theoretical Considerations

The co-design methodology is central in reconciling code theoretical properties (rate, distance, girth) with the practical movement primitives available in neutral atom hardware. The use of commuting APMs aligns code structure directly with hardware constraints, a paradigm shift from conventional code design dominated by abstract properties with little regard for physical implementation feasibility.

The results underscore that high-rate qLDPC codes are compatible not just with asymptotic overhead savings but with actionable performance at the crucial moderate block sizes accessible in the near term (several hundred to a few thousand qubits). The efficient, parallelizable syndrome extraction and high-throughput, low-latency hierarchical decoder also demonstrate direct avenues toward real-time, online quantum error correction in future quantum processors.

Outlook and Future Research Directions

The findings indicate several clear research directions and open problems:

• Extension to Logical Computation: While the current work targets quantum memory, the integration of these codes into architectures supporting full logical computation (with fault-tolerant gates and circuit surgery) requires optimized surgery gadgets and logical operator realization with minimal space-time overhead.
• Further Exploration of Code Families: The trade-offs in the affine-permutation design space—including systematic search for optimal combinations with lifted/balanced product codes—may yield codes with even more favorable parameters.
• Advanced Decoding Algorithms: The hierarchical decoder approach may benefit from incorporation of recent neural or machine-learning-based decoders, which offer improved speed-accuracy trade-offs, potentially mitigating the bottleneck associated with rare fallback to exact IP solvers.
• Physical Realism in Noise Models: Extensions to fully realistic circuit noise including idling and atom loss, and possible adaptation to other quantum hardware platforms, will be necessary for benchmarking practical fault-tolerant architectures.

Conclusion

This work provides a rigorous demonstration that ultra-high-rate qLDPC codes, precisely co-designed with hardware movement constraints and paired with high-accuracy decoding stacks, can achieve logical error rates and syndrome extraction time budgets consistent with future large-scale quantum processing. These results map a clear path towards practical, low-overhead, fault-tolerant quantum computation on neutral atom arrays and highlight the critical role of hardware-aware quantum code design in bridging the gap between theory and scalable experimental realization.