A Neutral-Atom Quantum Compiler with Application-Specific Layout and Hub-Assisted Shuttling

Abstract: Compiling arbitrary-connectivity NISQ circuits onto monolithic single-zone neutral-atom devices is constrained by a finite interaction range and a minimum separation between simultaneously addressable sites. Under the minimum-separation constraint, the SWAP-only configuration of our pipeline does not return a schedule within a practical time budget on a range of circuits, including circuits as small as nine qubits. We address this with hub traps, a small number of dynamically placed empty traps that serve as transit waypoints, together with a per-gate rule that chooses between SWAP-based routing and hub-mediated shuttling. We evaluate the compiler on seventeen benchmarks using analytic estimates of execution time and a per-layer fidelity proxy, comparing against a placement-matched baseline and against ablations of our own pipeline. Hub traps make these otherwise-unsolved circuits compile in seconds to minutes and remove SWAP gates entirely on every completed circuit, so their role is to enable routing rather than only to optimize fidelity. The benefit is concentrated on routing-dominated circuits and is absent on routing-free ones, which we separate by the structure of the interaction graph. On the most routing-dominated circuit the fidelity proxy improves by up to three orders of magnitude over the placement-matched baseline. The gain comes primarily from eliminating SWAP overhead, as the absolute fidelities there remain low.

• The paper presents a two-step quantum compiler that optimizes qubit placement and hub-assisted shuttling, effectively eliminating SWAP gates in routing-dominated circuits.
• It employs a dynamic cost model and A* path planning to address blockade radius, exclusion zones, and collision avoidance in neutral-atom devices.
• Empirical evaluations on NISQ circuits demonstrate significant fidelity improvements and scalability benefits compared to traditional SWAP-only methods.

A Neutral-Atom Quantum Compiler with Application-Specific Layout and Hub-Assisted Shuttling

Introduction and Context

This work presents a compilation framework for neutral-atom quantum processors, targeting constraints fundamentally different from static-coupling hardware such as superconducting qubits. In neutral-atom systems, two-qubit gates are constrained by a Rydberg-mediated finite interaction range (blockade radius) as well as a strict minimum atom separation for addressability and motion, while shuttling atoms between traps allows for more flexible, albeit complex, routing. The paper introduces a two-step quantum compiler that leverages these physical features: it optimizes qubit placement specifically for each application, and then generates executable schedules using a hub-assisted shuttling mechanism to eliminate reliance on SWAP gates.

Constraint Modeling and Hardware Abstraction

The compiler's constraint model integrates three principal considerations: (a) only qubits within the blockade radius can enact a direct $\mathrm{CZ}$ gate, (b) there is a strict minimum separation between occupied traps, and (c) atom transport operations must respect exclusion zones and collision avoidance during movement.

Figure 1: The compiler's constraint model illustrating (a) feasible $\mathrm{CZ}$ interactions, (b) minimum required separation, and (c) allowed atom transport primitives.

A monolithic single-zone device is assumed, with a set of static "home" traps initially occupied by data atoms (qubits) and a configurable number of dynamically placed, initially empty "hub" traps that act as transit waypoints.

Compilation Pipeline: Placement and Hub-Assisted Routing

A modular two-step pipeline forms the core of the approach:

1. Placement Optimization: Given a quantum circuit, an application-specific, continuous 2D placement is sought that brings high-interaction qubit pairs close together while satisfying the minimum-separation constraint. An interaction graph is extracted from the input circuit, and the optimizer minimizes the (normalized) correlation between interaction weight and geometric distance.
2. Transport-Aware Transpilation: Placement is followed by insertion of hub traps, which are chosen based on midpoints of long-range $\mathrm{CZ}$ pairs and filtered for feasibility. The transpiler then synthesizes a schedule by dynamically choosing, at each two-qubit gate that cannot be executed in-place, between SWAP chains (when possible) and shuttling through hubs.

   Figure 2: Visual summary of the two-step compilation workflow: placement and blockade radius selection (step 1), followed by hub trap allocation and gate schedule generation (step 2).

Hub Trap Heuristic and Scheduling Strategy

Effective hub trap placement is central to the compiler's ability to eliminate SWAPs. Candidates are generated at midpoints (or on endpoint-centered rings for flexibility) of long-range $\mathrm{CZ}$ pairs, and selected greedily to maximize proximity to endpoints and coverage, subject to separability constraints.

Figure 3: The hub placement heuristic generates and filters candidates from the geometry of long-range $\mathrm{CZ}$ pairs, maximizing endpoint proximity and respecting geometric exclusion.

For routing decisions, the transpiler uses a cost model that balances circuit execution time with cumulative gate and shuttling infidelities. When a direct gate is not feasible, all possible SWAP and shuttling options are evaluated: the path with the lowest cost is chosen, and "eviction" protocols are possible (e.g., temporarily moving idle atoms to vacate a hub). Shuttling distances are efficiently computed using pairwise A* precomputation on a grid with exclusion zones.

Figure 4: All-pairs grid-based A

path precomputation encodes collision-free shuttling distances, enabling efficient transpilation with hub traps.*

Empirical Evaluation on NISQ Circuits

The compiler is benchmarked on a suite of seventeen NISQ circuits with 9–39 qubits, encompassing both highly local and strongly routing-dominated interaction graphs. Detailed metrics include SWAP count, shuttle count, circuit depth, estimated execution time, and a fidelity proxy that accumulates gate errors, shuttle infidelity, and decoherence per time layer. The physical operating point is fixed for meaningful comparison.

Figure 5: The placement optimizer returns circuit-dependent normalized blockade radii, which, together with the fixed physical operating conditions, set the absolute scale of the compiled device.

The resource breakdown highlights the compiler's key achievement: for all successfully compiled benchmarks with nontrivial routing requirements, the hub-enabled pipeline entirely eliminates SWAP gates, replacing them with a comparatively small number of shuttles. In the most routing-dominated benchmarks, such as $\mathrm{heisenberg\_16}$ (3081 $\mathrm{CZ}$, 669 SWAPs in baseline) and $\mathrm{sqrt\_18}$ (898 $\mathrm{CZ}$, 402 SWAPs in baseline), the SWAP overhead in baseline methods is replaced by 91 or 50 hub shuttles, respectively, improving the cumulative fidelity metric by three orders of magnitude.

Figure 6: Per-benchmark fidelity ratio of the proposed pipeline vs. two Qiskit-based SWAP-only baselines, demonstrating especially significant gains for routing-dominated circuits.

Figure 7: Breakdown of synthesized resources, with zero SWAP gates (top), moderate shuttle counts (middle), and comparable or fewer layers (bottom) for the proposed method compared to SWAP-only pipelines.

The adder_9 example illustrates a typical case: most $\mathrm{CZ}$ gates are absorbed by placement, while the few remaining nonlocal interactions are realized via minimal shuttling through strategically positioned hubs.

Figure 8: Application-specific layout and hub-assisted routing for the adder_9 benchmark; direct $\mathrm{CZ}$0s are mapped by proximity, long-range ones are executed via shuttling through hubs.

Regime Distinctions and Enabling Role of Hub Traps

The empirical analysis divides the circuits into distinct structural regimes based on their interaction graphs:

• Routing-free: All $\mathrm{CZ}$1s are intra-blockade; placement alone suffices and all pipelines perform identically.
• Routing-dominated: Placement cannot resolve all interactions; without hubs, SWAP-only transpilers fail to return a schedule within practical time (even for circuits as small as 9 qubits). With hubs, compilation completes in seconds to minutes and omits SWAP gates.
• Boundary cases: Some circuits depend on placement seed or display structural transport closures; further work is required to classify them.

Hub traps are not an incremental fidelity optimization. For numerous circuits—even small ones—they are structurally essential to reach a solution under the minimum-separation constraint, transforming otherwise intractable routing into solvable problems. Detailed ablation studies demonstrate this qualitative shift.

Robustness to Shuttle Fidelity and Parallelism Assumptions

A sweep over per-shuttle infidelity values ($\mathrm{CZ}$2) confirms that the order-of-magnitude gain in routing-dominated circuits persists even for conservative shuttle fidelities. In more modest cases, the advantage narrows and may invert if the shuttle is highly noisy, as expected.

Figure 9: Robustness of the proposed pipeline's advantage under pessimistic per-shuttle infidelity assumptions, with routing-dominated gains retained.

Assuming parallel shuttling (multi-atom moves) further reduces execution time up to 22%, particularly on larger or more parallelizable instances, but does not change the primary qualitative conclusions.

Theoretical and Practical Implications

This work delivers several implications:

• Compilation Theory: Incorporating auxiliary hubs and a per-gate SWAP-vs-shuttle cost model introduces a hybrid paradigm, bridging "placement-centric" and "movement-centric" strategies with explicit modeling of minimum-separation and addressability—often underemphasized in abstraction-driven literature.
• Neutral-Atom Algorithms: Locally optimized, application-aware placements paired with dynamic hub allocation allow NISQ-era neutral-atom hardware to circumvent a fundamental class of infeasibility barriers, increasing circuit class coverage for quantum hardware experiments.
• Benchmarking: The structural separation between routing-dominated and placement-resolvable circuits provides guidance for future compiler benchmarking and informs the design of quantum algorithm benchmarks for specific hardware platforms.
• Scalability: As atom array sizes increase, the hub-mediated shuttling model can, with further extensions to placement heuristics and transport modeling, scale to accommodate more complex devices—motivating integration with fault-tolerant movement schemes and possibly even crossbar-style architectures.

Future work should focus on quantifying long-range interaction ratios to develop regime classifiers, enhancing placement strategies to avoid structural failures, and more closely matching movement-centric compilation frameworks for head-to-head evaluation.

Conclusion

The presented two-step neutral-atom compiler establishes hub traps as essential enablers for scalable circuit transpilation under realistic device constraints, achieving zero SWAP routing on otherwise unschedulable instances and significant improvements in fidelity and compilation tractability for routing-dominated circuits. The benefit is regime dependent, persisting under conservative error models, and highlights the crucial interplay between hardware constraints, physical movement, and quantum compilation architecture.