Search Smarter, Not Harder: A Scalable, High-Quality Zoned Neutral Atom Compiler (2512.13790v1)

Abstract: Zoned neutral atom architectures are emerging as a promising platform for large-scale quantum computing. Their growing scale, however, creates a critical need for efficient and automated compilation solutions. Yet, existing methods fail to scale to the thousands of qubits these devices promise. State-of-the-art compilers, in particular, suffer from immense memory requirements that limit them to small-scale problems. This work proposes a scalable compilation strategy that "searches smarter, not harder". We introduce Iterative Diving Search (IDS), a goal-directed search algorithm that avoids the memory issues of previous methods, and relaxed routing, an optimization to mitigate atom rearrangement overhead. Our evaluation confirms that this approach compiles circuits with thousands of qubits and, in addition, even reduces rearrangement overhead by 28.1% on average. The complete code is publicly available in open-source as part of the Munich Quantum Toolkit (MQT) at https://github.com/munich-quantum-toolkit/qmap.

• The paper introduces the Iterative Diving Search (IDS) algorithm, enabling efficient memory usage and goal-directed search in large zoned architectures.
• The paper demonstrates a mean 27.1% reduction in rearrangement time, successfully compiling circuits with up to 5000 qubits and over 300 parallel gates.
• The paper employs relaxed routing optimization that enhances parallel atom movement while balancing constraints like ghost-spot avoidance and non-crossing rules.

Scalable, High-Quality Compilation for Zoned Neutral Atom Quantum Architectures

Introduction and Motivation

Zoned neutral atom quantum devices leverage site-resolved trapping and manipulation of atoms within spatially organized architectures to facilitate high-fidelity two-qubit entangling gates and major scalability potential. As experimental implementations push toward thousands of qubits and highly parallel gate operations, the compilation of quantum circuits for these hardware platforms faces acute challenges. Chiefly, the mapping of abstract algorithms to zoned architectures involves combinatorial constraints—including non-crossing and no-ghost rules in atom movement—making scalable, quality-aware compilation a nontrivial search and optimization problem.

Standard approaches, motivated by the need to minimize decoherence-induced errors, target minimal rearrangement overhead—i.e., reducing the time atoms spend in movement between logic zones. Prior solutions, including state-of-the-art routing-aware placement algorithms built atop A* search, deliver lower rearrangement counts at the expense of exponential memory growth as parallelism increases. These methods become infeasible for instances with more than a few hundred qubits or a few dozen parallel entangling gates due to tensorial memory usage scaling, precluding their application to near-term devices.

Algorithmic Contributions

The paper introduces a compilation method tailored for scalability while maintaining, and in many cases improving, the quality metrics of interest for zoned neutral atom devices. The method comprises two central contributions: the Iterative Diving Search (IDS) algorithm and a relaxed routing optimization.

Iterative Diving Search

IDS is designed as a heuristic-guided, depth-first search inspired by, but distinct from, A* traversal. Where A* systematically explores partial placements in a best-first fashion, accumulating substantial memory requirements due to broad frontier storage, IDS traverses the search space in a much more memory-efficient, goal-directed manner. At each search step, IDS selects the most promising child (per the heuristic) to expand, diving deep toward a goal state. Only a bounded set of alternative partial solutions is held in a priority queue, limiting the search's memory footprint and avoiding the exhaustive breadth characteristic of A*. If a leaf is reached, the search restarts from the next-best partial solution, and this process continues for a prespecified number of trials to balance quality and compute effort.

Crucially, this strategy retains the advantages of cost and heuristic design from the prior state-of-the-art: these functions are crafted to prioritize placements yielding maximal parallel movement potential while respecting non-crossing, preservation, and ghost-spot constraints. The reduced search space and focused traversal allow IDS to operate solely with quality-optimized heuristics rather than those that balance between solution speed and result optimality.

Relaxed Routing Optimization

While routing the atom movements between zones, existing methods enforce strict row and column orders to avoid ghost-spot formation during parallel rearrangement steps. The relaxed routing modification introduced in this work lifts this constraint selectively: by permitting the reorder of rows or columns after specific pick-up/drop-off actions (while maintaining ghost-spot avoidance), parallelism is enhanced. For rearrangements involving large zone distances or many qubits, relaxed routing allows more atoms to be shuttled in a single rearrangement step, decreasing cumulative overhead. The method incorporates a trade-off: for shorter rearrangements, the extra offset movements may outweigh the gains from increased parallelism; thus, the compiler dynamically selects the optimal routing strategy per case based on empirical movement profile models.

Experimental Results

Comprehensive evaluation is performed on a range of circuit instances from MQT Bench, including highly parallel gate structures relevant for neutral atom platforms (e.g., graphstate circuits with up to 5000 qubits and 306 parallel entangling gates per layer). The core quality metric is the total rearrangement-induced execution time, directly proportional to circuit fidelity loss due to decoherence.

Analysis reveals several key quantitative results:

• Scalability: The IDS compiler successfully compiles all tested circuits with up to 5000 qubits and 300+ parallel gates, whereas the state-of-the-art approach fails with memory exhaustion for circuits above a few hundred qubits or ~40 parallel gates.
• Quality Improvement: Across benchmarks where both methods succeed, IDS consistently reduces rearrangement time overhead, yielding a mean improvement of 27.1%. For highly parallel instances (e.g., graphstate circuits), improvements exceed 45%.
• Augmented Gains with Relaxed Routing: The relaxed routing strategy further decreases rearrangement time, realizing total improvements of 28.1% over previous bests, with the largest gains on wide, parallel workloads.
• Resource Usage: Compilation times remain practical (seconds to minutes), and memory use is tightly controlled by design, in sharp contrast to the rapid scaling of existing approaches.

Practical and Theoretical Implications

This work enables the practical compilation of large-scale quantum circuits matching the hardware parallelism and connectivity offered by neutral atom devices, without sacrificing placement or routing quality. Fine-grained control over movement scheduling translates directly to higher fidelity and lower error rates, facilitating execution of deep or wide circuits essential to quantum error correction, quantum simulation, or variational eigensolvers.

Theoretically, the IDS paradigm demonstrates how domain-specific cost structures can be captured effectively in goal-directed, memory-constrained heuristic search, rather than relying on exhaustive best-first methods whose compute and memory requirements render them impractical for large problem instances. The interplay between strict and relaxed dynamic constraint enforcement in routing yields further insight into balancing local optimality (per-move minimality) and global optimality (minimal total rearrangement time) when hardware operation primitives exhibit nonlinear overheads.

Future Directions

The refinement and generalization of IDS hold promise for further extensions. Potential avenues include:

• Adapting IDS for dynamic compilation settings, reacting to mid-circuit atom loss or measurement feedback.
• Co-designing error mitigation techniques in tandem with rearrangement-aware compilation.
• Extending relaxed routing concepts to hybrid architectures featuring multiple entanglement/storage/measurement zone topologies.

Moreover, the modularity of cost/heuristic specification in IDS suggests that advances in stochastic/learning-based search guidance can be integrated without loss of scalability.

Conclusion

By introducing Iterative Diving Search and relaxed routing, the paper presents a compiler capable of scaling to zoned neutral atom quantum architectures with thousands of qubits and maximizing hardware utility. The methods yield substantial reductions in rearrangement overhead versus the state-of-the-art, enabling new experimental and algorithmic regimes for large-scale, parallel neutral atom quantum computation (2512.13790).