NeuroRing: Scaling Spiking Neural Networks via Multi-FPGA Bidirectional Ring Topologies and Stream-Dataflow Architectures

Abstract: Spiking neural networks (SNNs) are a promising paradigm for energy-efficient event-driven computation, but large-scale SNN execution remains challenging because sparse spike communication and synchronization can dominate runtime. Existing solutions across CPU, GPU, ASIC, and FPGA platforms offer different trade-offs between programmability, efficiency, and scalability. To address this gap, we present NeuroRing, a modular and scalable SNN accelerator based on a stream-dataflow architecture and a bidirectional ring topology, implemented in High-Level Synthesis (HLS) on programmable FPGAs. NeuroRing supports modular single- and multi-FPGA deployment and is compatible with existing SNN workflows through integration with the NEST simulator. We evaluate NeuroRing on the cortical microcircuit benchmark and a Sudoku constraint-satisfaction workload. Results show that NeuroRing preserves the key activity statistics of the NEST reference model, achieves faster-than-real-time execution of the full-scale cortical microcircuit with a real-time factor (RTF) of 0.83, exhibits meaningful strong and weak scaling, and provides competitive energy efficiency on two programmable FPGAs. These results position NeuroRing as a flexible and scalable platform for both neuroscience simulation and broader event-driven applications.

• The paper presents NeuroRing, a modular FPGA-based accelerator that leverages a bidirectional ring topology to enable faster-than-real-time SNN simulation with 73 nJ per synaptic event.
• The design employs paired stream-dataflow kernels and High-Level Synthesis to flexibly scale across single- and multi-FPGA deployments while interfacing with the NEST simulator.
• Extensive evaluation shows that NeuroRing preserves neural dynamics and efficiently scales for dense cortical microcircuits and constraint satisfaction tasks.

NeuroRing: Multi-FPGA Stream-Dataflow Architecture for Scalable SNN Simulation

Introduction

Spiking Neural Networks (SNNs) are increasingly leveraged for event-driven computation due to their inherent energy efficiency and biological realism. Large-scale execution of SNNs, however, poses substantial challenges because spike-based communication and synchronization can dominate computational cost, particularly in dense cortical microcircuit models. Various hardware platforms—CPUs, GPUs, ASICs, FPGAs—have been explored for SNN acceleration, each presenting unique trade-offs. The "NeuroRing" framework establishes a modular, scalable, and energy-efficient SNN accelerator built on a bidirectional ring topology, enabled by stream-dataflow processing and implemented via High-Level Synthesis (HLS) on FPGAs. NeuroRing interfaces directly with the NEST simulator and supports both single- and multi-FPGA deployments with backend-agnostic compatibility.

NeuroRing Architectural Overview

The NeuroRing core comprises paired stream-dataflow kernels—NeuroRing and SynapseRouter—instantiated as Compute Units (CUs) that communicate via intra-device AXI streams. All cores operate concurrently, overlapping computation and communication. The NeuroRing CU consists of an NPU, synapse-list fetch engine, and spike recorder. The NPU implements an 8-lane pipelined floating-point processing architecture for neuron-state updates and spike generation, maintaining neuron state variables in partitioned on-chip memory to maximize parallel access.

Figure 1: Architecture of the NeuroRing core, detailing the dataflow kernels and NPU/accumulator layout.

Synaptic event packets are sorted and routed through left/right ring streams, minimizing communication latency and balancing load. The SynapseRouter kernel receives spike event packets and either consumes or forwards them, leveraging eight parallel accumulators for delay-indexed synaptic updates using fast URAM packing. Synchronization tokens are used to enforce ring progress and preclude deadlock.

NeuroRing’s bidirectional ring topology facilitates scalable deployment across multiple FPGAs. Cores are interconnected via left/right streams internally, while boundary Aurora kernels enable full-duplex serial communication between FPGAs, preserving routing semantics and ensuring system-level modularity.

Figure 2: Bidirectional ring topology and experimental setup, illustrating intra- and inter-FPGA communication.

The architecture is backend-agnostic, operating on a synapse-list abstraction that is easily generated from the NEST simulator or other SNN workflows. Neuron models and capacity, synapse-list sizes, and resource allocation are configurable, driven by hardware resource constraints and the application profile.

Experimental Evaluation

NeuroRing was synthesized for AMD/Xilinx Alveo U55C FPGAs (target frequency: 300 MHz) and evaluated in both single- and dual-FPGA configurations. Neural workloads, including the cortical microcircuit benchmark and Sudoku CSP task, were generated in NEST and fed to NeuroRing via Python runtimes.

Correctness and Activity Preservation

Extensive correctness validation against the NEST software reference was conducted for the full-scale cortical microcircuit (77,169 neurons, $\sim$0.3B synapses). NeuroRing reproduced the characteristic layer-wise raster patterns and spiking statistics—firing rate, coefficient of variation, and Pearson correlation—in both excitatory and inhibitory populations.

Figure 3: Layer-wise raster plots of the cortical microcircuit, comparing NEST and NeuroRing outputs.

Figure 4: Layer-wise statistical comparison for full-size cortical microcircuit across firing rate, CV, and correlation.

Statistical agreement confirms that NeuroRing preserves the key dynamics of the reference model, with minor discrepancies traceable to hardware-level numerical and synchronization variances.

Architectural Trade-Offs and Performance Scaling

Design-space exploration established that lowering neuron capacity per core—increasing parallelism—yields improved real-time performance and reduced energy per synaptic event, though at the expense of higher total power due to greater core instantiation. The best-performing configuration achieved an RTF of 0.83 (faster-than-real-time), 73 nJ/synaptic event, and robust scaling across two FPGAs.

System scalability was quantified under strong and weak scaling regimes:

• Strong Scaling: Fixed workload distributed over increasing hardware units showed sublinear speedup due to intra-ring and inter-FPGA communication overhead. NeuroRing outperformed the CPU (Dardel) baseline in power and energy efficiency at comparable RTFs.
• Weak Scaling: Proportional growth in workload and resources revealed non-ideal scaling attributable to post-routing clock frequency shifts and inter-FPGA synchronization penalties. Nevertheless, energy per synaptic event remained favorable relative to software baselines.

State-of-the-Art Comparison

Direct comparison to leading SNN simulation platforms demonstrated that NeuroRing matches or exceeds real-time execution rates for the full-size cortical microcircuit at competitive energy costs (RTF: 0.83, Energy: 73 nJ/synaptic event). NeuroRing is more energy-efficient than GPU/CPU platforms and achieves a balance of programmability, scalability, and performance not seen in large ASIC or FPGA clusters.

Constraint Satisfaction Applications

NeuroRing’s applicability beyond neuroscience was validated via Sudoku CSP workloads, structurally mapped as winner-takes-all SNNs. All benchmark instances were solved to completion in under 0.6 seconds end-to-end latency, with SNN execution under 0.07 seconds and platform power at 20.8 W. Energy per synaptic event was higher due to reduced event counts but still documented stable solver performance.

Theoretical and Practical Implications

NeuroRing addresses the scalability bottlenecks in large-scale SNN computation by leveraging stream-dataflow modularity and a bidirectional ring topology, enabling flexible execution on standard FPGA hardware. The architectural abstraction layer decouples core processing from simulator-specific workflows, facilitating both neuroscience research and generic event-driven workloads. Energy efficiency and faster-than-real-time execution make NeuroRing suitable for dense microcircuit simulation and CSP domains, opening avenues for neuromorphic hardware in practical AI inference, real-time simulation, and accelerated modeling.

From a theoretical perspective, NeuroRing demonstrates that modular ring topologies and parallel stream-based compute organization can surmount dense spike communication bottlenecks. This architecture template is extensible to other neuron models and event-driven algorithms, supporting further exploration of bio-realistic computation and real-time solution of constraint-encoded problems. Integration with HLS enables rapid hardware adaptation, and backend-agnostic compatibility supports diverse research workflows.

Conclusion

NeuroRing advances the state-of-the-art in scalable, energy-efficient SNN simulation on FPGAs through a modular stream-dataflow architecture and bidirectional ring topology. The approach delivers real-time performance and architectural flexibility for neuroscience and CSP workloads, positioning FPGAs as viable platforms for research and event-driven applications. Future developments may extend NeuroRing’s application scope, adapt neuron models, and optimize ring communication for larger cluster deployments, propelling practical neuromorphic computing in AI and scientific research.