Quantum Circuit Cutting: Complexity and Optimization

Abstract: The current noisy intermediate-scale quantum (NISQ) era is characterized by substantial errors and noise, which limit the practical feasibility of deep, many-qubit circuits. To address these constraints, quantum circuit cutting has emerged as a promising tool. Recently, there has been significant research on methods for performing such cutting effectively. In this work, the duality between quantum circuits and classical graphs - specifically, directed acyclic graphs (dags) - is leveraged to analyze the complexity of finding an optimal circuit-cutting configuration that minimizes the number of cuts. After developing a rigorous graph-theoretic framework, the complexity of identifying cut locations that partition a given quantum circuit into smaller fragments is characterized. The corresponding graph-combinatorial task is then defined, and the resulting partition problem is shown to be NP-complete. Furthermore, even a simplified version of the problem, restricted to circuits composed only of one- and two-qubit gates, is shown to be NP-complete. Finally, based on these constraints, an algorithm grounded in satisfiability modulo theories (SMT) is proposed to find optimal cuts when the number of qubits per partition is bounded. This work therefore provides a complexity-theoretic characterization of cut placement and a practical solver for bounded-size decompositions.

• The paper establishes a NP-completeness characterization of optimal circuit cutting through a formal graph theoretic framework.
• It maps quantum circuits to directed acyclic graphs using tensor networks and edge duplication, enabling efficient decomposition.
• The SMT-based solver provides provably optimal clustering for bounded-edge cuts, setting a baseline for scalable multi-QPU systems.

Quantum Circuit Cutting: Complexity and Optimization

Abstract and Motivation

This work provides a comprehensive graph-theoretic analysis of quantum circuit cutting—specifically for timelike (wire) cuts—addressing the algorithmic and complexity-theoretic underpinnings of distributing quantum algorithms across multiple quantum processing units (QPUs) in the NISQ regime. The authors establish a formal correspondence between quantum circuits and legal directed acyclic graphs (dags), wherein circuit cutting is mapped to edge duplication in the graph representation. The main contributions are twofold: a rigorous NP-completeness characterization of the optimal circuit cutting problem and a practical satisfiability modulo theories (SMT) solver for bounded-size decompositions.

Quantum Circuits, Tensor Networks, and DAG Formalism

The paper adopts a tensor network viewpoint, making precise the circuit–graph correspondence by representing quantum circuits as legal dags. Vertices correspond to quantum operations (unitaries, preparations, or measurements), and edges track the logical flow of qubits. Unitarity is preserved as every non-input/output vertex maintains equal in- and out-degree. Quantum circuit execution, therefore, maps to paths from input to output vertices. The tensor formalism naturally accommodates the decomposition of high-rank unitaries into lower-rank tensors (often via MPO or MPS representations), which simplifies the analysis of fragmentable circuits.

Circuit cutting, in this context, is concretely realized as an edge duplication operation (Definition 6), which severs a qubit’s trajectory, creating two new vertices and corresponding edges, preserving the ability to simulate the resultant clusters independently.

Figure 1: Evolution of a quantum state within a tensor network. The initial state tensor is enclosed by the blue dashed line, the output by the red dashed line, and the complete process by the green dashed line.

This formalism is critical for translating quantum circuit cutting into a problem amenable to algorithmic complexity analysis using well-established graph-theoretic techniques.

Circuit Cutting Protocol and Sampling Overhead

The cutting protocol is grounded in the application of local Pauli-basis decompositions to qubit wires, following the method described in [Bravyi, Smith, Smolin 2016] and formal developments in circuit knitting [cutting_Haram, HarrowLowe2025]. Each cut introduces an exponential classical post-processing cost proportional to the number of qubit cuts ($8^K$ for $K$ cuts). This motivates stringent minimization of the total number of cuts, as the quantum advantage can be rapidly lost to classical overhead even for moderate $K$.

The decomposition protocol is further constrained: only edge (qubit) cuts are permitted—in contrast to operator (vertex) cuts—since the latter incurs significantly higher overhead tied to entanglement robustness and unitary-specific decompositions.

Graph Duplication Problem and Complexity Classification

The circuit cutting optimization problem is formalized as the "Graph Duplication" (GD) decision problem: given a legal dag $G$, integers $k$ (max allowed inputs/outputs per cluster), $\alpha$ (max number of clusters), and $\beta$ (cut budget), is it possible to duplicate at most $\beta$ edges such that $G$ partitions into at most $\alpha$ clusters with each cluster obeying the input/output bounds and containing a valid input–output path?

The key formal results are as follows:

• Polynomial-Time Tractability for Constant $K$0: If both $K$1 (maximum number of cuts) and the number of connected components of $K$2 are constant, GD is solvable in polynomial time by brute-force enumeration of all possible edge duplications and clusterings.
• NP-completeness for Unbounded Cuts or Components: If either $K$3 or the number of components is unbounded, the problem becomes NP-complete, shown via reductions from 3-partition (a strong NP-complete problem). This NP-completeness persists even for circuits constructed solely from one- and two-qubit gates (2-legal dags), which are sufficient for universal quantum computation.

  Figure 3: The case $K$4. The dag shown is $K$5.

  

  Figure 5: The connected dag $K$6 used in the NP-completeness proof for the general (connected) case.

These hardness results rigorously delineate the boundary between optimally fragmentable circuits and those where cut placement is intrinsically intractable to optimize, except in restricted or small-scale settings.

SMT-Based Algorithmic Framework

To complement the hardness results, the authors introduce an SMT-based scheme that exactly encodes GD for moderate instance sizes and bounded $K$7. The solver expresses the partitioning and edge duplication constraints as logical predicates, minimizing the total number of duplications subject to cluster size and connectivity constraints. The SMT formalism allows flexible encoding of physical and architectural constraints and returns provably optimal solutions when tractable.

The solver is implemented atop Microsoft Z3, and is capable of outputting explicit circuit partitions and indicating optimal cuts, supporting circuit design automation in multi-device NISQ settings. By enforcing optional connectivity constraints within clusters, the framework is robust to a variety of physical topologies and resource requirements.

Figure 2: SMT-based partitioning of an entangled circuit, with color-coded clusters and a highlighted cut.

Implications and Future Directions

This work delivers a rigorous understanding of the limitations of circuit cutting as a means for extending quantum computational reach on constrained NISQ hardware. The main practical implication is that scalable quantum circuit knitting will inevitably confront computational intractability for optimal cut placement as systems scale, unless restricted to bounded cut regimes and specific graph topologies.

Theoretically, the reductions establish a new complexity-theoretic foundation for quantum-classical hybridization protocols. Practically, the SMT-based approach forms a baseline for comparison with heuristic, hardware-aware partitioning methods employed in real-world quantum toolchains.

Future research directions include characterizing the tractability frontier when $K$8 grows moderately with the circuit size (e.g., $K$9), developing approximate or heuristic solvers exploiting quantum circuit locality or structure, and tightening run-time bounds for practically relevant classes of circuits common in quantum chemistry or machine learning applications.

Conclusion

The paper establishes a compelling graph-theoretic framework for the study of quantum circuit cutting, characterizing the problem's computational complexity and proposing a practical solver grounded in satisfiability modulo theories. The results underscore both the promise and the inherent limitations of circuit fragmenting protocols as applied to NISQ-era quantum computation. This work lays a precise mathematical foundation for further study of quantum-classical hybrid architectures and the development of scalable quantum software stacks.