NISQ Devices: Noisy Intermediate-Scale Quantum

• NISQ devices are intermediate-scale quantum processors (50–100 qubits) that operate without full error correction, making them susceptible to decoherence and crosstalk.
• They utilize advanced noise modeling and error mitigation techniques—such as randomized compiling and zero-noise extrapolation—to optimize limited circuit depth and fidelity.
• These platforms enable practical experimentation in quantum simulation, variational algorithms, and benchmarking quantum advantage, guiding the transition toward fault tolerance.

Noisy Intermediate-Scale Quantum (NISQ) Devices are quantum processors of intermediate scale, typically accommodating 50–100 qubits (potentially up to a few hundred), that operate without full quantum error correction. The “noisy” designation highlights their intrinsic susceptibility to decoherence, imperfect control, measurement infidelity, and correlated noise such as crosstalk, resulting in fundamental limits to circuit depth and fidelity. While NISQ devices are not expected to deliver large-scale quantum speedups in the absence of full fault tolerance, they serve as critical platforms for experimental exploration of quantum simulation, sampling, variational algorithms, and error mitigation techniques (Preskill, 2018).

1. Hardware Characteristics and Error Sources

NISQ devices are constructed predominantly from superconducting circuits or trapped ions, hosting O(10²) physical qubits with inter-qubit connectivities determined by device topology (e.g., heavy-hex lattices or all-to-all architectures for ions). Key error mechanisms include:

• Gate errors: Typical two-qubit gate error rates are in the neighborhood of $10^{-3}$–$10^{-2}$, corresponding to per-gate fidelities between 90% and 99%. Single-qubit gates achieve higher fidelities, often above 99.9% (Preskill, 2018).
• Readout errors: Measurement error per qubit is typically at the percent level, and inhomogeneous across the device (Dasgupta et al., 2021).
• Crosstalk: When gates are executed in parallel on nearby qubits, correlated errors (crosstalk) arise, often dominating the uncorrelated component when device layouts are dense (Heng et al., 2024).
• Decoherence: Characterized by $T_1$ (energy relaxation) and $T_2$ (dephasing) times, generally 20–200 μs for superconducting devices and up to seconds for trapped ions, manifesting as a fundamental limit to the achievable circuit depth (Dasgupta et al., 2021).
• Temporal and spatial drift: Device properties, including gate fidelities and coherence times, can fluctuate significantly across both time (hours to months) and spatially across a chip, with Hellinger distance measures between calibration distributions ranging up to 1.0 (no histogram overlap), undermining reproducibility (Dasgupta et al., 2021, Dasgupta et al., 2023).

The cumulative effect is that the maximum reliable circuit depth $G$ is strictly bounded by error probability $p$, with $G_{\max} \approx 1/p$; for $p\approx 10^{-3}$, $G_{\max} \lesssim 10^{3}$ entangling operations (Preskill, 2018, Dasgupta et al., 2021).

2. Noise Modeling, Benchmarking, and Stability

Noise in NISQ devices is most frequently modeled using quantum channels acting after each gate or at discrete time steps:

• Depolarizing channels: $$\mathcal{E}_{\text{DP}}(\rho) = (1-p) \rho + \frac{p}{3}(X\rho X + Y\rho Y + Z\rho Z)$$, parameterized by error rate $10^{-2}$0 (Dahlhauser et al., 2020).
• Readout error models: Bit-flip channels, symmetric or asymmetric, are fit to calibration data (Dahlhauser et al., 2020).
• Crosstalk and correlated errors: Simultaneous randomized benchmarking (SRB) quantifies error amplification due to parallel gate execution, with the crosstalk metric $10^{-2}$1; values $10^{-2}$2 are indicative of correlated noise (Heng et al., 2024, Dasgupta et al., 2021).
• Stability metrics: Temporal and spatial drifts are quantified via the Hellinger distance $10^{-2}$3 between histograms of fidelity metrics across time or device regions; values up to 1.0 reflect severe instability (Dasgupta et al., 2021, Dasgupta et al., 2023).

Resource-aware noise characterization schemes decompose circuits into small subcircuits for individually tailored noise modeling; model predictions are validated against experiment via total variation distance $10^{-2}$4, with fine-grained models reaching $10^{-2}$5–$10^{-2}$6 for 20-qubit GHZ states (Dahlhauser et al., 2020).

3. Quantum Algorithmic Strategies for NISQ Devices

The limited circuit depth and error budget drive the development of quantum algorithms explicitely tailored for the NISQ regime:

• Variational Quantum Eigensolver (VQE): Hybrid quantum-classical procedure using shallow, parameterized circuits to approximate molecular eigenstates, leveraging error tolerance in the classical optimization loop; successful on 2-qubit instances of quantum chemistry with active space reduction and readout mitigation (Preskill, 2018, Gao et al., 2019).
• Quantum Approximate Optimization Algorithm (QAOA): Uses low-depth (few-layer) alternations of mixer and problem Hamiltonian unitaries. For $10^{-2}$7 layers, circuits are within the NISQ feasibility window (Preskill, 2018).
• Classical optimizer selection: Robust, gradient-free optimizers such as ImFil or SnobFit are necessary to contend with noisy, non-differentiable cost landscapes induced by NISQ-level noise (Lavrijsen et al., 2020).
• Amplitude estimation and numerical integration: Classical phase estimation-based approaches are replaced by maximum-likelihood (MLQAE) families of shallow, parallelizable circuits, reducing depth by 5–10× and enabling practical implementation on 2–4 qubit regimes (Yu et al., 2020).
• Quantum neural networks and machine learning: Shallow, data-reuploading circuits, patch-based quantum GANs, and dissipative QNNs (CP maps) achieve resilience to hardware errors and have demonstrated parity or mild advantage over similarly sized classical models for vision tasks and unitary learning (Mandadapu, 2024, Beer et al., 2021).

Device-specific circuit transpilation, error-aware circuit approximation (removal/merging of multi-qubit gates), and circuit partitioning for noise avoidance yield up to 60% fidelity improvement and extend the algorithmic reach of NISQ processors (Wilson et al., 2021, Waring et al., 2024).

4. Error Mitigation Protocols

Given the absence of full error correction, NISQ computation relies on error mitigation protocols:

• Noise tailoring (randomized compiling): Converts coherent gate errors into stochastic Pauli noise, leaving the ideal evolution unchanged (Preskill, 2018).
• Zero-noise extrapolation: Artificially amplifies gate errors (e.g., by stretching gates) and extrapolates measurement results back to the zero-noise limit (Preskill, 2018).
• Stochastic and Richardson-extrapolated QEM: Models the full computation as a continuous Lindblad evolution and inserts quasi-probabilistic recovery operators, suppressing error to two orders beyond the bare circuit for both digital and analog simulations; further variance reduction is achieved by Richardson extrapolation to account for model mismatch (Sun et al., 2020).
• Resource pruning: Dynamically partitioning the device to exclude components exceeding error thresholds maintains utility as the hardware ages, yielding up to 52% improvement in gate fidelity for 50-qubit CNOT chains (Waring et al., 2024).
• Instruction barriers for crosstalk suppression: Serializing entangling gates reduces correlated errors due to crosstalk by up to 3× in overall circuit fidelity, but must be balanced against increased circuit depth and consequent decoherence (Heng et al., 2024).
• Error-detecting codes: Small codes (e.g., four-qubit Bacon-Shor, repetition codes) flag error events without full overhead of fault-tolerant protocols (Preskill, 2018).

Mitigation strategies typically stretch the effective $10^{-2}$8 by factors of a few, but do not substitute for full error correction.

5. Benchmarks and Quantitative Metrics

Benchmarking and certification is essential due to device variability and context-dependent noise properties:

• Quantum Volume (QV): Standard benchmark combining circuit width, depth, gate fidelity, connectivity, and compile effectiveness. QV is the largest $10^{-2}$9 for which an $T_1$0-qubit, depth-$T_1$1 random SU(4) circuit yields heavy output probability consistently above 2/3. In practice, user-attainable QV lags vendor-reported QV by factors of up to 2–4, and is highly sensitive to device calibration, compiler optimization, and spatial qubit selection (Pelofske et al., 2022).
• Stability and reliability analyses: Longitudinal tracking of physical metrics (fidelity, duty cycle, addressability) via Hellinger distance and computed bounds on circuit output variation are necessary; in a 16-month, 127-qubit IBM device study, the empirical reliability metric fluctuated between 41% and 92%, versus the maximum allowable 2.2% for stability under the Bernstein-Vazirani protocol (Dasgupta et al., 2023).
• Hydrodynamics and many-body phases: NISQ devices enable simulation of dynamics (e.g., KPZ superdiffusion, Heisenberg transport) at system sizes ($T_1$2) and timescales previously inaccessible, with robust extraction of power-law transport exponents up to gate errors $T_1$3–$T_1$4 (Richter et al., 2020).

Table: Example NISQ Device Metrics

Property	Typical Value	Reference
Two-qubit error	$T_1$5–$T_1$6	(Preskill, 2018, Dasgupta et al., 2021)
Readout error	1–5%	(Dahlhauser et al., 2020, Dasgupta et al., 2021)
$T_1$7	$T_1$8	(Preskill, 2018)
QV (user)	$T_1$9–$T_2$0	(Pelofske et al., 2022)
Drift Hellinger	0.3–1.0 (spatial, temporal)	(Dasgupta et al., 2021, Dasgupta et al., 2023)

6. Applications and Scientific Frontiers

Despite fidelity and depth restrictions, NISQ hardware is enabling investigation of previously intractable physical and computational phenomena:

• Quantum simulation: NISQ platforms are exploited as quantum simulators for many-body spin systems, hydrodynamics, and out-of-equilibrium dynamics, using trotterization or, for open systems, time-independent-depth Kraus-operator series circuits (Richter et al., 2020, Burdine et al., 2024).
• Quantum networking: NISQ-scale hardware can be re-purposed to simulate quantum network elements and error models in the event-driven framework, exploiting noise as a tool to replicate operational imperfections in communication channels (Riera-Sàbat et al., 10 Jun 2025).
• Many-body physics (MBL, DTC): The Sycamore device enables experimental realization of Floquet discrete time crystals in the MBL regime, with hundreds of cycles observable, validating underlying theoretical models (Ippoliti et al., 2020).
• Certification of quantum advantage: Early demonstrations of random circuit sampling establish “quantum supremacy” as an empirical milestone; ongoing benchmarks probe the classical intractability boundary (Preskill, 2018, Richter et al., 2020).
• Quantum information protocols: Bell inequality violation, with loophole closure tests and noise profiling at small scale (2–4 qubits), is feasible and robust to NISQ-level depolarizing noise (Naus et al., 2020).

7. Prospects, Limitations, and Transition to Fault-Tolerance

The NISQ era is considered a proving ground for quantum hardware and algorithms, with major open directions including:

• Lowering error rates: Fundamental scaling to fault-tolerant computation demands two-qubit fidelities well below $T_2$1 and radical improvements in connectivity and qubit stability (Preskill, 2018).
• Improved noise and stability metrics: Integration of real-time device characterization and reliability bounds into compilation and scheduling layers is critical for algorithmic reproducibility (Dasgupta et al., 2021, Dasgupta et al., 2023).
• Noise-adaptive partitioning and mapping: Dynamic subgraph selection and error-aware compilation extend hardware lifetime and maximize attainable fidelities (Waring et al., 2024).
• Transition to fault tolerance: Large-scale applications (e.g., prime factoring or realistic chemistry) will require millions of physical qubits to synthesize thousands of protected logical qubits, owing to surface code threshold constraints; only then will arbitrarily deep circuits be feasible (Preskill, 2018).

NISQ devices—by running shallow circuits of depth $T_2$2 with $T_2$3–$T_2$4 noisy qubits—offer the first window onto quantum algorithms in unreachable classical regimes. They facilitate foundational experimentation in hardware, software, noise-resilient algorithmics, and the study of quantum-classical computational boundaries, all of which inform the roadmap to scalable, fault-tolerant quantum computing (Preskill, 2018).