Fault-Tolerant Quantum Computing with Trapped Ions: The Walking Cat Architecture
Abstract: We propose a fault-tolerant quantum computer architecture for trapped-ion devices, which we call the walking cat architecture. Our blueprint includes a compiler, a detailed description of all the quantum error-correction protocols, a micro-architecture, a sufficiently fast decoder, and thorough simulations. The backbone of the architecture is a cat factory, producing cat states distributed throughout the machine, which are consumed to perform logical operations. The walking cat architecture is based entirely on a modern quantum error-correction approach called low-density parity-check (LDPC) codes. We identify promising instances of the walking cat architecture, such as (1) a simple architecture based on a single LDPC code, (2) a fast architecture based on fast logical gates relying on a [[70, 6, 9]] code, equipped with Clifford-frame tracking for any 6-qubit Clifford gate, and (3) a dense architecture based on a [[102, 22, 9]]] code encoding 22 logical qubits per memory block. Our dense architecture provides a design with 110 logical qubits executing about one million T gates per day using only 2,514 physical qubits. We estimate that the quantum Hamiltonian simulation of a Heisenberg model on 100 sites can be executed within one month with 10,000 physical qubits, including all shots required to achieve chemical accuracy, suggesting that such a device could enter the regime of classically intractable physics simulations. Our design relies on hardware components that have been experimentally demonstrated on small devices. We emphasize simplicity over hypothetical performance to facilitate the practical realization of this machine. Based on this approach, we believe that a fault-tolerant quantum computer with hundreds of logical qubits capable of running millions of logical gates can be built in the near term, providing a platform to explore a broad range of applications.
Summary
- The paper presents a fault-tolerant quantum computing blueprint using trapped-ion hardware and quantum LDPC codes.
- It details a three-layer architecture that translates high-level quantum algorithms into physical QCCD operations through modular components.
- Simulation results show logical error rates below 10⁻¹⁰, demonstrating practical scalability and robust error management.
Fault-Tolerant Quantum Computing with Trapped Ions: The Walking Cat Architecture
The "Walking Cat Architecture" presents a comprehensive, pragmatically motivated, fault-tolerant quantum computing (FTQC) blueprint for trapped-ion systems based on quantum LDPC codes. Distinguished by an end-to-end focus on engineering realism, explicit architectural layers, and detailed resource/simulation analyses, the work bridges the gap in the literature between abstract resource estimation and implementable FTQC with contemporary code families and ion trap hardware.
Architectural Overview and Abstraction Layers
The architecture is defined across three explicit layers: compiler, logical architecture, and micro-architecture—mapping quantum programs through logical instructions down to device-level QCCD operations. This layered abstraction is detailed in Figure 1.
Figure 1: Layers of abstraction in the Walking Cat FTQC, connecting program, compiler, error-corrected logical instructions, physical gates, and QCCD device operations.
At the top, the compiler decomposes high-level quantum algorithms into a sequence of logical operations. The logical architecture builds blocks around LDPC codes implementing fault-tolerant storage, Clifford gates, and measurement primitives; the micro-architecture maps logical instructions to transport and physical gates in the QCCD model.
Logical Architecture: Components and Organization
The core logical architecture modularizes computation into memory blocks (LDPC-based), magic factories for non-Clifford resources, cat factories for high-fidelity logical measurements, Bell factories for remote cat stitching, and a global qubit factory for loss recovery. Figure 2 provides a schematic overview.
Figure 2: High-level layout showing interconnected blocks—memory (M), magic factories (T), cat factories (C), Bell factories (B), and a global qubit reservoir (Q) for loss correction.
Memory blocks (Figure 3) integrate four parallel rows: data, ancilla for syndrome extraction, “beacon” qubits for loss detection, and a transport “highway.”
Figure 3: Memory block with rows for data, ancilla (error correction), beacon (loss detection), and highway (fast ancilla shuttling).
Magic factories (Figure 4) extend the memory design with an additional ancilla for magic state injection, enabling the preparation of logical H-type or T-type resource states necessary for universal computation.
Figure 4: Magic state factory built atop the memory block structure, with specialized ancilla for H-state preparation.
Cat factories (Figure 5) efficiently generate and verify large cat states via repeated rounds of stabilizer measurement and cyclic ancilla shifts, crucial for scalable, robust logical measurement.
Figure 5: Cat factory, employing sequential cat state preparation, multi-round verification, and cyclical rotation of cat qubits.
This modularity enables parallel operation and massive scaling, supporting hundreds of logical qubits and millions of logical gates with precise error management.
LDPC Code Families: Three-Ring Framework and Performance
A central technical advance is the unified “three-ring” architectural framework supporting several families of quantum LDPC codes: Generalized Bicycle (GB), Bivariate Bicycle (BB), and Cyclic Hypergraph Product (HGP) codes. Codes such as [[102,22,9]], [[70,6,9]], and [[54,2,10]] are used for memory and magic factory blocks, combining high code rates and structural regularity for efficient syndrome extraction and ancilla scheduling.
Syndrome extraction exploits fast transport via cyclic shifts—enabling logical clock cycles (“SEC,” syndrome extraction cycles) on the order of tens of POC (physical operation cycles).
Loss and Leakage Handling
Loss and state leakage are managed directly in hardware, crucial for trapped-ion devices. Each data qubit is paired with a “beacon” for loss detection after two-qubit layers within each SEC (see Figure 6), and leakage is corrected using teleportation-based protocols. This tight coupling with hardware-level operations ensures that rare events such as chain loss or cascading leakage are localized and corrected, bounding logical error even at scale.
Figure 6: Teleportation-based data qubit leakage detection for robust in-place recovery.
Detailed simulation and Markov modeling quantify requirements for local/global reservoirs and loading zones needed for robust system-wide loss resilience.
Magic State and Logical Measurement Factories
Unlike prior approaches reliant on topological code-based distillation, this work defines two resource-efficient magic state factory protocols leveraging directly the native properties of selected LDPC codes: one using a MEK (Meier-Eastin-Knill) distillation scheme; another relying on strongly transversal logical H operations. Comprehensive analysis (from low-level logical circuits to adaptive error correction) quantifies success probabilities, error rates, and average runtimes for each factory.
Logical measurements employ cat states and adaptive protocols (EDM, ECM, Viterbi), balancing error suppression with throughput. The architecture guarantees that any accessible logical Pauli is measurable within the operational width of the supporting cat factory, and Clifford gates are implemented via frame tracking whenever possible.
Figure 7: Circuit decompositions for T and T† gates, using cat-state-based measurements and logical resource states.
Resource Estimates and Performance
Detailed resource allocation (Figures 10 and 11) balances physical qubits across memory, magic, cat, and Bell factories to optimize throughput for up to 1M–10M T gates per day on 100–300 logical qubits, using only a few thousand physical qubits.
Figure 8: Resource allocation breakdown for architectures supporting hundreds of logical qubits and up to 10M T gates per day.
Figure 9: Tradeoff curve for logical qubits versus magic state throughput in single-code architectures.
Simulations at operating points , , (consistent with demonstrated hardware) yield logical error rates per SEC well below . Memory-reload overhead from qubit loss remains negligible with judicious sizing of local and global reservoirs.
Micro-architecture, Transport, and Qubit Routing
Transport overhead is minimized using regular, parallel shuttling patterns—cat qubits are delivered and returned efficiently to their respective factories (outer loop routing, accounted for in transport qubit allocation). The micro-architecture accounts for layout, qubit movement costs, and clocking constraints, matching the timescales demonstrated in current QCCD hardware.
Decoding: Real-Time, Streaming Beam Search
A scalable, windowed, streaming variant of the beam search decoder is developed, aligning decoding latency with hardware constraints and enabling real-time operation. Empirical simulation over SECs shows that reaction/decoding time per SEC consistently remains under practical thresholds, and logical error rate is within a factor of two of global decoding.
Implications, Practicality, and Outlook
The Walking Cat architecture demonstrates that, for trapped-ion hardware within current or projected experimental capabilities, it is possible—using modern quantum LDPC codes—to achieve FTQC with hundreds of logical qubits and millions of gates. The explicit focus on modular simplicity, regularity, and hardware-realistic error models marks a significant step toward practically building useful ion-trap quantum computers beyond NISQ.
Notably, the architecture’s flexibility in code choice, logical operation accessibility, and qubit routing supports not only quantum chemistry simulation (e.g., a Heisenberg model on 100 sites) but also a breadth of future quantum applications. Further, the design admits easy integration of new code families or application-specific modules as hardware and quantum algorithms advance.
Conclusion
This work delivers a thorough architectural prescription for scaling trapped-ion FTQC, grounded on hardware-demonstrated fidelities and modern LDPC encodings. By addressing the entire stack—from logical gate specification through error correction, physical transport, resource modeling, and online decoding—the Walking Cat architecture stands as a robust reference design for near-term construction of practical, large-scale quantum computers with trapped ions. The explicit separation of abstraction layers and the uniform code-based logical architecture will serve as a template for development and optimization of future FTQC platforms, both in incremental hardware demonstrations and in theoretical resource analysis.
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What is this paper about?
This paper explains a plan for building a reliable, large-scale quantum computer using trapped ions. The authors call their design the “Walking Cat” architecture because it uses special quantum states called “cat states” that are created in one place and then “walk” (are moved) around the machine to help perform safe, error‑resistant operations.
The big idea is to turn today’s noisy quantum machines into fault‑tolerant ones—systems that can run millions of steps without crashing—by combining simple hardware that already works in labs with modern error-correcting codes and a practical layout.
What are the key questions the paper tries to answer?
The paper focuses on a few main goals:
- How can we design a trapped-ion quantum computer that corrects errors fast enough to run big programs?
- Can we build it using components and techniques that have already been demonstrated in small devices?
- What’s the simplest way to organize the machine so it’s easier to build, while still being powerful?
- How many qubits and how much time would common tasks (like chemistry simulations or factoring) actually take?
How does the architecture work? Methods explained simply
Think of the whole quantum computer as a small city:
- Memory blocks are neighborhoods where information is stored safely.
- Cat factories are workshops that make “cat states,” which are highly entangled groups of qubits—like a team that’s all synchronized (roughly “all zeros and all ones at the same time”). These cat states travel to where they’re needed to help perform precise measurements without spreading errors.
- Magic factories produce “magic states,” which are special ingredients needed to run a type of quantum operation called a T gate. You can think of magic states like batteries that power advanced moves.
- Bell factories make simple two-qubit entangled pairs used to stitch cat states together across long distances—like building bridges between neighborhoods.
- A qubit factory reloads fresh ions when some are lost, like a supply depot keeping the city running.
Behind the scenes, three layers keep everything organized:
- Compiler: Translates a high-level quantum program into a list of safe, error‑corrected steps.
- Logical architecture: Defines what error‑corrected operations exist (like safe measurements and T gates) and how to do them using resource states from the factories.
- Micro‑architecture: Maps these steps to real device actions on a trapped-ion chip (moving ions, performing gates, and measuring).
To design and test this, the paper uses a “moving‑qubit model.” Imagine the chip as a grid where ions can be moved, like cars on a road. Operations include:
- Transport steps (moving ions around quickly),
- Single- and two-qubit gates,
- Measurements that also check for ion loss or leakage (when a qubit slips out of the valid state space).
Real-world issues like noise, leakage, and loss are included. The authors also build a fast “decoder” (like spell‑check for errors) that runs continuously so mistakes are corrected before they pile up.
Finally, the architecture is built around modern quantum LDPC codes. These are like advanced seatbelts for information: they spread data across many physical qubits so errors can be found and fixed, while still keeping connections sparse and simple. The authors introduce and use three specific codes with different trade‑offs:
- [[70, 6, 9]] for flexible memory and magic production,
- [[54, 2, 10]] for fast cat‑based measurements,
- [[102, 22, 9]] for dense storage (22 logical qubits per memory block).
What did they find, and why is it important?
Here are the main takeaways, explained plainly:
- Practical size and speed: With only about 2,500 physical qubits, they can store roughly 110 logical (error‑corrected) qubits and run about one million T gates per day. With around 7,600 physical qubits, they can reach over 200 logical qubits and more than 10 million T gates per day.
- Near‑term feasibility: All core hardware parts (moving ions, performing gates, measuring, checking for loss/leakage) have been demonstrated in smaller experiments. The design favors simplicity over fancy but risky features, making it more realistic to build soon.
- Efficient memory: Their dense [[102, 22, 9]] LDPC code packs 22 logical qubits into just 102 physical qubits. Compared to “surface codes” (a popular alternative), this is dramatically more qubit‑efficient for the same error protection.
- Flexible operations: They can do fast logical measurements and track many logical operations in software (“frame tracking”), reducing the need to physically perform certain gates each time.
- Full workflow: They specify a compiler, the logical instruction set, the error-correction routines, a micro‑architecture, and a streaming decoder—an end‑to‑end blueprint, not just a rough estimate.
- Realistic noise model: They include not only gate errors, but also ion loss and leakage, and show how to detect and fix both while continuing the computation.
- Example applications:
- Physics simulation: With about 10,000 physical qubits, they estimate simulating a 100‑site Heisenberg model in roughly one month—likely beyond classical computers.
- Factoring demonstration: A configuration with ~13,000 physical qubits could factor certain 30‑bit numbers in less than a day, far beyond the tiny demonstrations done so far.
Why this matters: Moving from small, noisy devices to reliable, fault‑tolerant systems is the big leap needed to make quantum computing truly useful. This blueprint suggests that the leap might be possible sooner and with fewer qubits than many people thought.
What are the broader implications?
- A practical path forward: By emphasizing simplicity, modularity, and already‑proven hardware, this design could help build the first truly useful quantum computers sooner.
- Unlocking new science: Hundreds of logical qubits running millions of gates opens the door to problems that classical computers struggle with—like certain materials simulations, optimization tasks, and chemistry problems.
- General-purpose machine: While the paper discusses factoring and physics simulations, the architecture is meant to be flexible, not specialized. It could support a wide range of quantum applications.
- Foundation for growth: The approach can be scaled up step by step—adding more memory blocks or more factories—while keeping the system manageable.
In short, the “Walking Cat” architecture shows a clear, realistic plan to build a fault‑tolerant trapped‑ion quantum computer that’s powerful enough to matter and simple enough to actually make.
Knowledge Gaps
Knowledge gaps, limitations, and open questions
Below is a consolidated list of concrete gaps and unresolved questions that, if addressed, would strengthen, validate, or extend the proposed walking cat architecture.
- Mapping to device physics: quantify the overhead and fidelity impact when translating the moving‑qubit model to a realistic QCCD stack (merge/split chains, zone availability, junction transit limits, motional mode management), removing the simplification that transport and computation cannot overlap and that long‑distance “highway” transport is instantaneous.
- Noiseless loss/leakage readout assumption: characterize realistic false‑positive/false‑negative rates for loss/leak detection, their back‑action, and how misclassifications propagate through decoding and FT guarantees; derive tolerable bounds.
- Leakage reset model: validate that a practical leakage reset produces the assumed I/2 state with the quoted error rate and latency in Ba+; quantify residual state populations, repumping/cooling overheads, and the effect on duty cycle and logical error rates.
- Highway transport design: specify a physical highway architecture (trap geometry, junction throughput, maximum concurrent shuttles, heating) and determine minimum transport speeds needed to meet the one‑month and “M T‑gates per day” targets; assess thermal budgets and recooling requirements.
- Cat factory throughput and error model: provide explicit factory circuits, verification protocols, acceptance probabilities, correlated error analysis (from shared operations, verification, and routing), and maximum cat size achievable at p≈1e−4 before performance collapses; quantify time/area trade‑offs.
- Stitched cat states via Bell links: model the composite error channel of stitched cats (including Bell‑pair generation/distribution, routing delays, and entanglement swapping), and show that correlated and biased errors do not violate fault‑tolerant measurement conditions; determine distance‑dependent latency/infidelity.
- Magic state factory details and comparisons: give full circuit specifications and performance for MEK‑in‑code and cat‑based Clifford factories (yields, acceptance, output error rates vs input p, latency, space), and compare to cultivation/surface‑code factories under the same device and noise assumptions.
- Code specifications and scalability: publish explicit parity‑check matrices (H_X, H_Z), check weights/degrees, and syndrome schedules for [[102,22,9]], [[70,6,9]], [[54,2,10]]; characterize decoding performance under the moving‑qubit noise with loss/leak (FER vs rounds), and estimate thresholds/pseudothresholds and finite‑size scaling.
- Decoder practicality: detail the streaming decoder architecture (algorithms, dataflow, memory footprint), worst‑case latency/throughput under continuous load, tail‑latency management to avoid stalling logical operations, and integration of flagged loss/leak information; provide correctness guarantees with asynchronous frame updates.
- Compiler and scheduler: specify contention‑aware scheduling (cat/bell/magic factories, routing, QEC cycles), deadlock avoidance, prioritization policies, reactivity to stochastic factory failures, and online re‑compilation strategies when factory yields fluctuate.
- Clifford frame tracking limits: quantify conditions under which 6‑qubit frame‑tracked Cliffords remain “quasi‑instantaneous” (latency, classical control timing), and what is required to extend this to higher‑arity Clifford gates without inflating latency or error.
- Parallelism constraints: reconcile the assumed “one POC for any disjoint set of operations” with real QCCD limits (number/location of gate/measure zones, laser beam multiplexing, crosstalk); determine actual concurrency ceilings and their impact on throughput.
- Noise realism: include coherent/correlated errors (crosstalk, spectator excitations, transport‑phase errors), spatial/temporal correlations, and drifts; evaluate robustness via randomized compiling or bias‑tailored codes; provide sensitivity to non‑depolarizing error channels.
- Loss propagation through 2Q gates: validate the worst‑case loss‑propagation model experimentally; assess whether gate engineering can confine loss or flag it more locally, and quantify the performance gains if achievable.
- Reloading logistics and reservoirs: specify the routing and control policies for replenishing local reservoirs from the global pool under congestion, minimum loading rates vs reservoir sizes from the Markov model, and the impact of reloading pauses on logical error; account for sympathetic cooling and species management.
- Cooling and heating budgets: model heating during shuttling/segmentation and cooling times (including multi‑species coolant logistics), integrate into the POC/transport timing assumptions, and quantify the effect on throughput and error.
- Measurement primitives: define the composite 4‑outcome (0/1/lost/leaked) measurement implementation (zones, optics, detection times), its crosstalk and error modes, and the penalty for requiring loss/leak readout after every measurement.
- Ancilla reuse policy: establish reinitialization and “decontamination” protocols for measured/verified ancillas (post‑leakage, after heavy photon scattering), lifetime limits before replacement, and the effect on factory throughput and ion budget.
- Application‑level transparency: release full circuits and resource breakdowns for the Heisenberg‑100 and Shor‑30 benchmarks (T‑count/depth, Clifford depth, shots, idle overheads, factory utilization, routing), and compare against the best classical solvers to substantiate “classically intractable” claims.
- Sensitivity margins: quantify acceptable deviations in p, leak, loss, POC and transport times to still achieve 1–10M T/day and month‑scale runs; identify the dominant bottlenecks and provide performance contours.
- Scaling to 100k+ physical qubits: outline interconnect topology evolution, factory scaling laws, decoder scaling (compute/memory), and control‑system architecture needed to maintain throughput and latency at larger scales.
- End‑to‑end FT guarantees: provide rigorous FT analyses (pseudothresholds, malignant set counts, or matching‑based bounds) that include cat‑based measurements, loss/leak handling, and frame tracking, under realistic correlated noise.
- Floorplanning and congestion: present concrete floorplans/routing schedules for the example configurations, show non‑blocking operation when memory QEC, magic delivery, and inter‑block measurements occur concurrently, and quantify congestion headroom.
- Micro‑architecture completeness: give detailed timing/control protocols for components not fully specified (Bell factories, qubit factory control, routing/backbone/highway implementation, junction operation) and verify they meet timing with noise budgets.
- Operational overheads: account for calibration, drift tracking, retuning, and ion replacement downtime in throughput estimates; quantify their duty‑cycle impact.
- Comparative positioning: provide apples‑to‑apples resource and performance comparisons with leading surface‑code and neutral‑atom LDPC architectures under matched noise/timing assumptions to identify crossover regimes.
- Hardware prerequisites and demonstrations: enumerate and prioritize the experimental milestones needed (99.999% 1Q, 99.99% 2Q at scale, 200 μs POC under load, reliable leak reset and loss/leak readout, fast shuttling with low heating), and define acceptance tests that validate architectural assumptions.
- Error bias and code matching: analyze whether cat‑based measurements introduce Pauli‑bias and whether biased LDPC codes or tailored distillation would reduce overheads.
- Retry‑aware scheduling: design buffering and scheduling policies that absorb stochastic failures (cat/Bell verification rejects, magic rejects) without starving memory QEC or violating timing of logical operations; size buffers accordingly.
- Classical control latency: budget classical processing latencies for mid‑circuit feedback (frame updates, adaptive MEK steps, decoder outputs), determine maximum tolerable latencies before idle‑induced logical errors dominate, and propose mitigation.
- Inter‑block connectivity at scale: quantify added latency/error for distant joint measurements via stitched cats as a function of distance and traffic; determine throughput limits when many inter‑block measurements are requested simultaneously.
- Reproducibility: release code (compilers, decoders, simulators), code libraries for the new LDPC codes, and datasets to enable independent replication and stress‑testing of the claimed performance.
Practical Applications
Below is a concise mapping from the paper’s technical contributions to practical, real-world applications. Items are grouped by deployment horizon and annotated with likely sectors, potential tools/products/workflows, and key assumptions/dependencies that influence feasibility.
Immediate Applications
- Sector: Quantum hardware (ion traps); Software/Tooling
- Apply the paper’s hierarchy/modularity/regularity/simplicity (HMRS) blueprint to guide chip floorplans, control stacks, and component tiling (memory blocks, cat/magic/Bell factories, qubit factory).
- Products/workflows: Architecture playbooks; co-design templates; layout generators for cyclic-shift routing; resource dashboards per component.
- Dependencies: Availability of QCCD-compatible transport; buy-in to component-based tiling and resource state interfaces; classical control integration.
- Sector: Quantum hardware (ion traps)
- Deploy post-selected physical cat states and cat-based Pauli measurements as a practical alternative to lattice surgery ancillas for stabilizer measurements and logical joins.
- Products/workflows: Cat factory modules; cat-state quality monitors; stitching routines using Bell states.
- Dependencies: Two-qubit gate error ≈1e−4; fast, high-yield cat generation (enabled by 99.99%+ fidelities); transport pathways to memory/magic blocks.
- Sector: Quantum hardware; Manufacturing/Operations
- Integrate loss/leak detection/reset, local/global reservoirs, and reloading logistics (with Markov-chain sizing) to keep components from stalling.
- Products/workflows: Reload schedulers; reservoir inventory managers; loss propagation mitigation policies.
- Dependencies: Reliable loss/leak detection tied to readout; reload interface at chip edges; predictable loading rates and background gas handling.
- Sector: Quantum hardware (ion traps)
- Use the moving-qubit model for internal planning (operation times, transport cost, leakage/loss, locality) and scheduling benchmarks before device-level micro-architecture mapping.
- Products/workflows: Digital twins for QCCD; transport-aware schedulers; latency/throughput calculators using POC/transport timing.
- Dependencies: Approximate fidelity-to-time mapping (e.g., 200 μs POC, 10 μs transport step); vendor-specific constraints.
- Sector: Quantum software/compilers
- Implement compiler backends that emit logical instructions (magic consumption, Pauli measurements) and frame tracking for multi-qubit Clifford gates (up to 6-qubit) within memory blocks.
- Products/workflows: Passes for Pauli-based decomposition; Clifford-frame trackers; codegen libraries for LDPC-backed memories.
- Dependencies: Stable logical instruction cost models; alignment with decoder latencies and cat/magic factory throughput.
- Sector: Quantum error correction/decoding software
- Integrate the paper’s fast streaming decoder and latency profiling into real-time control loops.
- Products/workflows: Decoder microservices; reaction-time watchdogs; backpressure handling for logical operations.
- Dependencies: Deterministic latency envelopes; compatibility with leakage/loss reports; control-stack bandwidth.
- Sector: Academia; Benchmarks/Standards
- Use the new LDPC codes (e.g., [[102,22,9]], [[70,6,9]], [[54,2,10]]) and the unified framework (GB/BB/HGP) as benchmarks for decoders, compilers, and hardware tests.
- Products/workflows: Open code libraries/datasets; cross-lab benchmark suites; reproducible E2E pipelines.
- Dependencies: Reference implementations; access to noise models and timing; community adoption.
- Sector: Cloud quantum services; Education
- Offer early-access logical qubits (tens to ~100) with guaranteed error budgets and cat/magic factory-backed operations for developers and courses.
- Products/workflows: APIs for logical operations (measurements, magic consumption); quotas based on T-gates/day; lab modules for LDPC/cat-based FTQC.
- Dependencies: Stable throughput (e.g., ~1M T/day class); SLAs for reload and decoding; DevEx tooling.
- Sector: Policy/Standards; Cybersecurity
- Use the moving-qubit model and leakage/loss-aware metrics to inform standards on “logical performance” reporting, bridging lab demos to policy timelines.
- Products/workflows: Readiness scorecards; conformance tests; guidance on loss/leakage reporting.
- Dependencies: Multi-vendor consensus; credible third-party benchmarks; regulator engagement.
- Sector: Materials/chemistry research (academia/industry)
- Run tractable, mid-scale models (e.g., Heisenberg instances on random degree-7 graphs with ~100 sites) as exploratory studies to validate workflows ahead of larger campaigns.
- Products/workflows: Pauli-based simulation libraries; sampling orchestration (shots for chemical accuracy); hybrid analysis pipelines.
- Dependencies: Access to ~10k physical qubits; one-month-class runtime windows; verified mapping from target Hamiltonians to logical instructions.
Long-Term Applications
- Sector: Materials science; Energy; Manufacturing
- Leverage 100–200 logical qubits and million‑T/day throughput to simulate complex spin systems, amorphous materials (e.g., 3D glasses), catalysts, and battery components beyond classical limits.
- Products/workflows: Quantum workflows integrated with HPC; parameter-sweeping campaigns; uncertainty-quantified outputs for R&D pipelines.
- Dependencies: Sustained error rates (p≈1e−4, low leak/loss); robust compiler/decoder stacks; scalable magic/cat capacities.
- Sector: Pharmaceuticals; Healthcare R&D
- Use early FTQC simulation to probe active-site models and fragment-based approaches that are challenging for classical methods.
- Products/workflows: Hybrid QM/MM with quantum cores; Pauli-based Hamiltonian kernels; validation against experimental observables.
- Dependencies: Problem mappings that fit 100–200 logical qubits; chemistry-specific compilation optimizations; validated error budgets for chemical accuracy.
- Sector: Cybersecurity; Finance; Government
- Near-term: factor ~30-bit integers to validate end‑to‑end FTQC stacks; longer-term: refine resources and timelines for cryptosystems at risk, guiding PQC adoption strategies.
- Products/workflows: Cryptanalytic testbeds; CISOs’ risk dashboards tying FTQC metrics to PQC milestones; red‑team exercises.
- Dependencies: Magic factory scaling; gate counts/latencies; realistic paths from ~13k to 100k+ physical qubits for larger keys.
- Sector: Quantum cloud; Software ecosystems
- Establish a developer ecosystem around logical instructions, Clifford-frame tracking, and LDPC-aware scheduling/verification.
- Products/workflows: SDKs targeting logical measurement primitives; conformance suites; portable IRs for Pauli-based computation.
- Dependencies: Vendor-neutral abstractions; stability of logical instruction costs; community governance.
- Sector: Quantum hardware (multi-vendor)
- Adapt walking-cat principles (cat factories, cyclic shifts, resource-state interfaces) to other platforms (neutral atoms, electron-on-helium) with transport or long-range coupling substitutes.
- Products/workflows: Platform-specific micro-architectures; interop testbeds; design libraries for non-local stabilizers.
- Dependencies: Viable transport/coupling primitives; leakage/loss control; layout-aware compilation.
- Sector: Supply chain; Manufacturing; Test & measurement
- Industrialize cat/magic/Bell factory calibration, yield tracking, and decoder QA as part of production test flows.
- Products/workflows: Automated calibration rigs; state-quality dashboards; decoder regression tests with latency SLAs.
- Dependencies: Robust metrology; traceable error budgets per component; standardized test patterns.
- Sector: HPC integration; Operations research
- Optimize orchestration of cat/magic production/consumption, transport paths, and shot accumulation to minimize time-to-solution.
- Products/workflows: Workflow schedulers aware of factories and reservoirs; reinforcement learning for routing; queueing models with POC/transport timing.
- Dependencies: Accurate runtime distributions; streaming-decoder latency tails; stable transport latencies.
- Sector: Education; Workforce development
- Train students and engineers using real-world architectural constraints (leakage/loss, moving-qubit model, factory throughput).
- Products/workflows: Course modules; lab exercises on scheduling/decoding; capstone projects on code design and compiler passes.
- Dependencies: Access to simulators and/or logical-qubit cloud pilots; open code/data artifacts.
- Sector: Standards/Policy; Safety and reliability
- Create norms for reporting loss/leakage rates, reload policies, decoder failure rates, and “logical uptime” to guide procurement and regulation.
- Products/workflows: Certification frameworks; audit procedures; incident reporting schemas for logical-level failures.
- Dependencies: Industry participation; reproducible metrics; alignment with international bodies.
- Sector: Analytics; Risk management (cross-industry)
- Tie capability forecasts (e.g., million‑T/day with ~10k qubits) to R&D portfolios, cybersecurity budgets, and product roadmaps.
- Products/workflows: Scenario models; sensitivity analyses to error rates/throughput; investment decision support.
- Dependencies: Transparent benchmarks; continuous updates from hardware progress; conservative uncertainty bounds.
- Sector: Algorithm research (academia/industry)
- Redesign algorithms to minimize T-gates and leverage fast Clifford frame tracking and join measurements enabled by cat states.
- Products/workflows: Library of LDPC/Pauli-optimized algorithms; cost models that reflect factory bottlenecks.
- Dependencies: Stable logical primitives; accurate cost estimates; collaboration with hardware teams.
- Sector: Advanced cryptography; Protocol design
- Explore early protocols that require modest logical qubit counts but strong guarantees from FTQC stacks.
- Products/workflows: Prototype verifiers; interactive proof circuits mapped to LDPC memories; evaluation harnesses.
- Dependencies: Reliable logical error rates (~1e−10 targets); protocol-specific gate counts; cloud integration.
Assumptions and dependencies common across many applications:
- Hardware performance: ≈99.99% two-qubit gate fidelity; ≈99.999% single-qubit fidelity; leakage ≈1e−5/POC; loss ≈1e−7/POC; transport steps ≈10 μs; POC ≈200 μs.
- Reliable loss/leakage measurement and reset; stable qubit reloading with sufficient reservoir capacity.
- Ability to move ions (cyclic shifts and highways) without excessive noise or congestion.
- Decoder throughput with small, well-characterized reaction times; software/hardware co-design to avoid stalls.
- Scalable cat and magic factory throughput to meet T-gate/day targets; validated compilers to Pauli-based logical instructions.
- Access to or development of micro-architectures mapping the moving-qubit model to specific device instruction sets.
Glossary
- Ancilla: An auxiliary qubit or register used to facilitate fault-tolerant operations or measurements. Example: "lattice surgery consuming large ancilla patches of surface codes"
- Bell factory: A subcomponent that produces Bell pairs to connect distant operations or stitch resource states. Example: "The stitching is performed using Bell states, produced in Bell factories and distributed to the cat factories."
- Bell state: A maximally entangled two-qubit state used for teleportation or stitching operations between components. Example: "The stitching is performed using Bell states, produced in Bell factories and distributed to the cat factories."
- Biplanar LDPC codes: A family of LDPC codes with checks embeddable on two planes; used as a comparative baseline for code rate/distance. Example: "biplanar LDPC codes of~\cite{bravyi2024high}"
- Bivariate Bicycle (BB) code: A quantum LDPC code construction defined via bivariate polynomials; part of the unified framework the architecture supports. Example: "bivariate bicycle (BB) codes~\cite{bravyi2024high}"
- Cat factory: A dedicated component that prepares cat states at scale for fault-tolerant measurements. Example: "The backbone of the architecture is a cat factory, producing cat states distributed throughout the machine, which are consumed to perform logical operations."
- Cat state: A multi-qubit entangled GHZ-like state used to implement fault-tolerant logical measurements. Example: "The resource states we rely on are physical cat states,"
- CCZ state: A three-qubit non-Clifford resource enabling CCZ (controlled-controlled-Z) operations via state injection. Example: "CCZ state production~\cite{yoder2025tour, webster2026pinnacle, cain2026shor}"
- Chemical accuracy: A target precision threshold in quantum chemistry simulations corresponding to ~1 kcal/mol. Example: "including all shots required to achieve chemical accuracy"
- Clifford-frame tracking: Software-level updating of the effective Clifford operations without applying them physically, reducing latency. Example: "equipped with Clifford-frame tracking for any 6-qubit Clifford gate"
- Clifford measurements: Measurements implemented in the Clifford framework (e.g., via stabilizers), often using entangled ancillas like cat states. Example: "cat-based Clifford measurements"
- Cyclic hypergraph product (HGP) code: A quantum LDPC code family formed from hypergraph products with cyclic structure. Example: "cyclic hypergraph product (HGP) codes~\cite{aydin2025cyclic}"
- Cyclic shift: A coordinated transport primitive moving a set of qubits around a closed loop, used throughout the architecture. Example: "The {\em cyclic shift} is one such transport operation during which a set of qubits move all together along a loop."
- Depolarizing noise: A common noise model that replaces a state with a maximally mixed state on the operation’s support with some probability. Example: "followed by depolarizing noise on their support."
- Fault-tolerant quantum computer (FTQC): A quantum computer that can reliably execute long computations by correcting errors throughout. Example: "require a fault-tolerant quantum computer (FTQC) capable of reliably executing tens of millions of gates on thousands of qubits"
- Fully connected model: An idealized error-correction simulation model assuming unrestricted qubit connectivity and full parallelism. Example: "In this section, we review the fully connected model"
- Generalized Bicycle (GB) code: An LDPC code family based on generalized bicycle constructions; supported by the unified framework. Example: "generalized bicycle (GB) codes~\cite{kovalev2013quantum}"
- Heisenberg model: A spin Hamiltonian used as a benchmark for quantum simulation of many-body physics. Example: "quantum Hamiltonian simulation of a Heisenberg model on 100 sites"
- Leakage: An error where a qubit leaves the computational subspace into higher levels, disrupting gate operations. Example: "We define a {\em qubit leakage} rate per POC."
- Leakage reset: An operation that returns a leaked qubit to the computational subspace (often to the maximally mixed state). Example: "Leakage reset"
- Lattice surgery: A technique in topological codes to perform logical operations by merging and splitting code patches. Example: "lattice surgery consuming large ancilla patches of surface codes"
- Low-density parity-check (LDPC) code: A sparse-graph error-correcting code enabling high-rate, low-overhead quantum error correction. Example: "low-density parity-check (LDPC) codes."
- Magic factory: A component that prepares high-fidelity non-Clifford resource (magic) states for implementing T/CCZ gates. Example: "logical magic states are generated in magic factories (T)"
- Magic state cultivation: A protocol class that iteratively improves magic-state fidelity using specific code layouts and operations. Example: "magic state cultivation~\cite{gidney2024magic, yoder2025tour, webster2026pinnacle, cain2026shor}"
- Meier, Eastin, and Knill (MEK) scheme: A specific magic state distillation protocol used to produce T states efficiently. Example: "referred to as the MEK scheme~\cite{meier2013magic}"
- Micro-architecture: The low-level implementation details and scheduling of device instructions for each logical component. Example: "a micro-architecture, a sufficiently fast decoder, and thorough simulations."
- Moving-qubit model: A refined architecture model that includes nearest-neighbor constraints, transport operations, loss, and leakage. Example: "we call the {\em moving-qubit model}, and detail fully in \cref{sec:The moving qubit model}."
- Pauli-based computation model: A computation paradigm where programs are implemented via Pauli measurements and magic states. Example: "This model of computation, called the {\em Pauli-based computation} model, introduced in~\cite{bravyi2016trading}"
- Pauli frame tracking: Software tracking of Pauli corrections instead of applying physical gates, reducing operation counts and latency. Example: "physical Pauli frame tracking~\cite{raussendorf2001one, knill2005quantum, riesebos2017pauli, litinski2019game, on2023multilayered, paler2014software}"
- Physical operation cycle (POC): A time unit in which one layer of concurrent computational operations can be executed. Example: "We refer to the concurrent implementation of a set of disjoint computational operations as a {\em physical operation cycle} or {\em POC}"
- Quantum Charge-Coupled Device (QCCD) architecture: A trapped-ion architecture that moves ions between zones for gates and measurements. Example: "The QCCD architecture has been validated experimentally on devices with up to 98 qubits"
- Qubit loss: An error where the physical carrier of the qubit is lost, necessitating reloading or replacement. Example: "We define a {\em qubit loss} rate per POC"
- Reservoir (global reservoir): A store of spare, freshly loaded qubits used to replace lost qubits across the chip. Example: "Moreover, we include a global reservoir that stores freshly loaded qubits until they are distributed to refill the local reservoirs."
- Stabilizer code: A class of quantum error-correcting codes defined by a commuting group of Pauli operators (stabilizers). Example: "All the quantum codes used in this paper are stabilizer codes."
- Surface code: A topological quantum error-correcting code implemented on a 2D lattice, often used with lattice surgery. Example: "topological codes like surface codes."
- Topological code: Codes whose logical information is protected by global topological properties of a lattice. Example: "in opposition to topological codes like surface codes."
- Trapped ions: A hardware platform where ions are confined and manipulated with electromagnetic fields for quantum computation. Example: "Our architecture for a trapped-ion FTQC"
- Walking cat architecture: The proposed end-to-end trapped-ion FTQC design centered on cat-state factories and LDPC codes. Example: "We propose a fault-tolerant quantum computer architecture for trapped-ion devices, which we call the walking cat architecture."
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