LDPC-cat codes for low-overhead quantum computing in 2D (2401.09541v2)

Abstract: Quantum low-density parity-check (qLDPC) codes are a promising construction for drastically reducing the overhead of fault-tolerant quantum computing (FTQC) architectures. However, all of the known hardware implementations of these codes require advanced technologies, such as long-range qubit connectivity, high-weight stabilizers, or multi-layered chip layouts. An alternative approach to reduce the hardware overhead of fault-tolerance is to use bosonic cat qubits where bit-flip errors are exponentially suppressed by design. In this work, we combine both approaches and propose an architecture based on cat qubits concatenated in classical LDPC codes correcting for phase-flips. We find that employing such phase-flip LDPC codes provides two major advantages. First, the hardware implementation of the code can be realised using short-range qubit interactions in 2D and low-weight stabilizers, which makes it readily compatible with current superconducting circuit technologies. Second, we demonstrate how to implement a fault-tolerant universal set of logical gates with a second layer of cat qubits while maintaining the local connectivity. We conduct a numerical brute force optimisation of these classical codes to find the ones with the best encoding rate for algorithmically relevant code distances. We discover that some of the best codes benefit from a cellular automaton structure. This allows us to define families of codes with high encoding rates and distances. Finally, we numerically assess the performance of our codes under circuit-level noise. Assuming a physical phase-flip error probability $\epsilon \approx 0.1\%$, our $[165+8\ell, 34+2\ell, 22]$ code family allows to encode $100$ logical qubits with a total logical error probability (including both logical phase-flip and bit-flip) per cycle and per logical qubit $\epsilon_L \leq 10^{-8}$ on a $758$ cat qubit chip.

• The paper introduces an innovative LDPC-cat code design that synergizes cat qubits with LDPC codes to reduce error correction overhead in quantum systems.
• It leverages 2D grid structures and low-weight stabilizers compatible with current superconducting circuits for practical, fault-tolerant operation.
• Numerical assessments demonstrate encoding of 100 logical qubits with error rates ≤10⁻⁸, underscoring the approach’s scalability and efficiency.

Review of "LDPC-cat Codes for Low-Overhead Quantum Computing in 2D"

The research paper proposes an innovative approach for reducing the overhead necessary for fault-tolerant quantum computing (FTQC) through a novel architectural design that synergizes cat qubits and Low-Density Parity-Check (LDPC) codes. This combination, referred to as LDPC-cat codes, is intended to address the challenges of scalability and hardware efficiency in the domain of quantum error correction.

Quantum LDPC codes are traditionally seen as an attractive paradigm due to their theoretical potential to decrease error correction overhead significantly. However, they have practical implementation challenges, especially concerning qubit connectivity and stabilization requirements. Generally, successful hardware realization demands long-range qubit connections and high-weight stabilizers. Meanwhile, cat qubits, which are bosonic qubits, inherently suppress bit-flip errors due to their noise bias, providing a promising alternative for phase-flip error correction when concatenated with classical LDPC codes.

In this paper, the authors propose a quantum architecture where phase-flip errors are corrected via LDPC codes, facilitating fault-tolerant computation with reduced hardware overhead. The architecture is based on two key elements:

1. Hardware Implementation Using 2D Grid Structures: By ensuring compatibility with existing superconducting circuit technologies, the proposed architecture requires only short-range interactions and low-weight stabilizers, which is crucial for practical implementation.
2. Constructing Logical Gates with Cat Qubits: A fault-tolerant universal set of logical gates can be implemented efficiently using a second layer of cat qubits. This maintains the local connectivity and exploits the intrinsic bias in cat qubits to protect against bit-flip errors, which are notably less frequent.

To substantiate the proposed architecture, the authors conduct a detailed numerical optimization of these codes, identifying those with high encoding rates and efficient error suppression capabilities. They report finding families of codes that exhibit both high performance and reduced hardware requirements.

Furthermore, the paper provides a thorough numerical assessment, contrasting the performance of these codes under circuit-level noise with different assumptions. Noteworthy results include:

• Assuming realistic physical error probabilities (in the example given, about 0.1%), the proposed code family $[165+8\ell, 34+2\ell, 22]$ can encode 100 logical qubits with a logical error probability per cycle that's kept exceedingly low at $\leq 10^{-8}$ on a 758 qubit chip.

The implications of this development are significant for practical and theoretical paradigms in quantum computing. Practically, this work aligns quantum error correction codes with current technological capabilities, potentially accelerating the development and deployment of quantum processors capable of solving classically intractable problems. Theoretically, this advances the understanding of error correction in quantum systems, particularly regarding quantum-to-classical code transitions enabled by cat qubit architectures.

This paper also opens the door to future advances, such as reconfigurable quantum processors utilizing LDPC-cat codes, optimized logical gate implementations, and improvements in qubit coherence times, all of which will further bridge theoretical quantum computing models with experimental realizations. These findings are expected to spark secondary research efforts focused on pushing the boundaries of quantum error correction efficiency through innovative uses of hybrid qubit technologies.