LightMat-HP: A Photonic-Electronic System for Accelerating General Matrix Multiplication With Configurable Precision

Abstract: Matrix multiplication is a fundamental kernel in large-scale artificial intelligence and scientific computing, but its performance on conventional electronic accelerators is increasingly constrained by memory bandwidth and energy efficiency. Photonic computing offers a promising alternative due to its ultra-high bandwidth, massive parallelism, and low power dissipation. However, most existing photonic systems are limited to low-precision computation because of analog optical modulation constraints and noise accumulation, which restricts their applicability in precision-critical workloads. To address this limitation, we propose LightMat-HP, a hybrid photonic-electronic computing system that enables end-to-end acceleration of general matrix multiplication with configurable computational precision. LightMat-HP adopts block floating-point (BFP) arithmetic to reduce computational complexity while enabling flexible precision-performance tradeoffs. To overcome the precision limitations of photonic devices, we propose a slicing-based photonic multiplication scheme that exploits the high accuracy of low bit-width photonic multiplication in combination with digital accumulation to achieve high-precision mantissa multiplication. A tile-based matrix multiplication dataflow is further designed to support matrices of arbitrary sizes. We experimentally validate LightMat-HP on a photonic computing prototype and evaluate its performance through large-scale simulations. The results demonstrate that LightMat-HP outperforms FPGA, GPU, and a state-of-the-art photonic accelerator across throughput, latency, and energy efficiency, particularly for small- and medium-sized matrix multiplications, owing to its highly parallel photonic architecture, efficient data movement, and slice-based BFP arithmetic.

• The paper introduces a hybrid photonic-electronic system leveraging block floating point arithmetic and mantissa slicing to achieve configurable-precision matrix multiplication.
• The method uses tile-based dataflow with mantissa slicing to align photonic constraints with high precision, demonstrating relative errors typically below 1% for 4–5 bit slices.
• System-level results show LightMat-HP outperforms CPU, GPU, FPGA, and other accelerators, achieving >6.6 TFLOPS peak throughput and 39.14 GFLOPS/W energy efficiency on large matrices.

LightMat-HP: Precision-Configurable Hybrid Photonic-Electronic Matrix Multiplication

Motivation and Context

Matrix multiplication remains central to numerical linear algebra and the performance-critical path of AI, HPC, and scientific simulation workloads. The escalating scale and complexity of deep learning models, especially foundation models, have led to increased emphasis on compute- and energy-efficient matrix multiplication engines. Conventional digital electronic architectures, despite aggressive scaling, are fundamentally limited by bandwidth, power density, and memory-wall constraints. Photonic computing, which performs analog computation in the optical domain, offers unique potential due to high bandwidth density, inherent parallelism, and low signal attenuation. However, practical deployment in high-precision workloads has remained elusive, as physical device nonlinearity and noise restrict native photonic computation to low-bitwidth domains (typically <8 bits).

Existing photonic approaches have lacked a systemic methodology for flexible, high-precision GEMM that can match the numerical requirements of DNN training and scientific computing. LightMat-HP addresses this gap with a hybrid electronic-photonic system that leverages block floating-point (BFP) arithmetic, mantissa slicing, and tile-based dataflow to enable configurable-precision matrix multiplication with robust numerical properties.

Numerical Formats and Photonic Arithmetic

Block floating-point (BFP) arithmetic provides a superior tradeoff between dynamic range and hardware cost. It assigns a common exponent to a block of values (tile) while performing fixed-bitwidth arithmetic on mantissas. This enables shared exponent scaling, reduces exponent handling circuitry, and naturally matches photonic processing constraints, where precision is bottlenecked not by arithmetic complexity but by ENOB (effective number of bits) imposed by device SNR and nonlinearity. The BFP approach is further coupled with operation slicing, where each high-bitwidth mantissa is decomposed into lower-bitwidth slices, matching the maximal reliable bitwidth of photonic multipliers (typically 3–6 bits).

Figure 1: A comparison of Floating Point 32 (FP32) and Block Floating Point (BFP) representations, highlighting exponent sharing and mantissa precision scalability.

Empirical results with custom photonic testbeds show that absolute error grows with operand bitwidth, but relative error remains stable (typically <1% for 4-5 bit slices). This validates both the upper-bound on bitwidth for atomic photonic multiplication and the use of digital post-accumulation to suppress zero-mean stochastic noise via the central limit effect.

System Architecture and Data Movement

The system integrates an electronic subsystem (for memory, scheduling, BFP<—>FP conversion, and accumulation) with a photonic subsystem (MZM-based photonic multipliers, WDM, and photo-detection), interconnected via high-speed DAC/ADC.

Figure 2: System-level schematic for intensity modulation using a Mach–Zehnder Modulator (MZM) as the photonic arithmetic primitive.

The architecture employs a modular tile-based dataflow. Input matrices are partitioned into configurable tiles; BFP encoding is performed per tile; mantissas are sliced and serially streamed to Photonic Processing Units (PPUs) that exploit intra-tile and inter-slice parallelism via wavelength and spatial multiplexing.

Figure 3: Photonic MZM arrays effect multiplication and addition primitives via cascaded modulation and WDM signal summation.

Parallelism is scalable via replication of PPUs, and tile sizing is co-optimized to fit on-chip SRAM and match photonic pipeline bandwidth.

Figure 5: (a) Block diagram of the complete LightMat-HP architecture showing electronic and photonic domains. (b) Detailed PPU structure with laser, mux/demux, and photodetection.

Mantissa Slicing and Precision Scalability

Photonic multiplication of two high-bitwidth mantissas is decomposed into multiple lower-bitwidth multiplications on slices, mapped to photonic hardware in space (more PPUs) or time (more cycles); digital accumulation reconstructs the high-precision result via shift-and-add.

Figure 7: Visual representation of (a) slice-based decomposition for two 10-bit mantissas, and (b) dataflow mapping to the photonic computing pipeline.

This architectural strategy provides natively configurable precision: increasing the number of mantissa slices increases numerical precision at the cost of more photonic operations (additional cycles/parallelism), with no need for higher photonic device precision.

Figure 9: Tile-based photonic matrix multiplication workflow—tiled partitioning, mantissa slicing, photonic-domain multiplication, and digital assembly.

Precision Modeling and Empirical Results

A precise error analysis shows three dominant error sources: FP-to-BFP quantization, stochastic photonic noise on each atomic multiplication (modeled as zero-mean Gaussian), and digital rounding on accumulation. Simulation and evaluation on a prototype platform demonstrate that for typical matrix sizes (16–1024), mantissa widths of 10 bits (with two 5-bit slices) yield relative $\ell_2$ errors consistently <$0.75\%$, and that relative error decays as $1/\sqrt{N}$, confirming the statistical averaging of uncorrelated photonic noise in large dot-products.

Figure 4: Error scaling for LightMat-HP as matrix size increases: relative error decreases, absolute error increases sublinearly.

Error is further suppressed by increasing mantissa width (increasing number of slices) or tile size. There is, however, a diminishing return once analog photonic precision is no longer the dominant error source.

Figure 6: Relative $\ell_2$ error as a function of mantissa precision and matrix size.

Comparative Performance and System-Level Results

Simulations with 100 PPUs (each 4-MZM, 100 GHz, and 4.096 GS/s RF electronics) and large-scale, full-stack modeling (including DRAM/SRAM bandwidths, DAC/ADC, and digital logic) show LightMat-HP saturates hardware and optoelectronic interface bandwidth at matrix sizes $> 256 \times 256$. The design outperforms (in latency, throughput, and energy efficiency) an Intel i5-12400F CPU (MKL), RTX 3060 GPU (cuBLAS), custom FPGA, and BITLUME—a recent SOTA photonic accelerator.

• LightMat-HP achieves peak throughput >6.6 TFLOPS and energy efficiency of 39.14 GFLOPS/W for $1024 \times 1024$ matrices.
• For small/medium matrices ($\leq 256 \times 256$), LightMat-HP delivers lower latency and higher throughput than all baselines.
• Compared to BITLUME, LightMat-HP exhibits 1.48x higher energy efficiency and up to 2.48x lower end-to-end latency.

  Figure 8: Simulated scaling of LightMat-HP energy efficiency as the number of PPUs increases, surpassing GPU efficiency beyond 100 photonic cores.

  

  Figure 10: Throughput, latency, and energy efficiency comparison across CPU, GPU, FPGA, and photonic accelerators.

The limiting system elements in area and power are now the DAC/ADC interface and MZM footprint—not photonic compute itself—indicating a key shift from computation-bound to conversion-bound system scaling.

Practical and Theoretical Implications

LightMat-HP demonstrates that by co-designing numerical formats, hardware slicing, and data movement, photonic computing can be elevated from low-precision MAC engines to general-purpose matrix multiplication suitable for both AI inference/training and scientific computing. The hybrid photonic-electronic approach effectively matches strengths: photonic for dense dot-products, digital for control, accumulation, and flexibility.

Practically, the architecture enables:

• Programmable gemm with selectable precision/configuration, suitable for ML, HPC, and DNN training.
• Large-scale parallelism via modular PPU replication, suitable for ASIC or chiplet integration.
• Graceful tradeoff between energy, throughput, and precision via tile and slice parameters.

Theoretically, the work advances error-bounded analog computing via noise-resilient digital-augmented architectures and suggests that further improvements will now be driven by advances in photonic device miniaturization, low-power DAC/ADC innovation, and photonic integration (e.g., 3DIC/ePICs).

Conclusion

LightMat-HP sets a new state-of-the-art for configurable-precision matrix multiplication in hybrid photonic-electronic systems, substantively outperforming prior architectures and matching or exceeding conventional digital platforms on several key metrics. Its architectural modularity, precision scalability, and robust error properties indicate viability for next-generation high-performance AI accelerators. Open challenges remain in further reducing optoelectronic interface costs and expanding photonic integration, which are essential for realizing large-scale deployment and matching the flexibility of modern digital tensor processors (2604.12278).