CapBench: A Multi-PDK Dataset for Machine-Learning-Based Post-Layout Capacitance Extraction

Abstract: We present CapBench, a fully reproducible, multi-PDK dataset for capacitance extraction. The dataset is derived from open-source designs, including single-core CPUs, systems-on-chip, and media accelerators. All designs are fully placed and routed using 14 independent OpenROAD flow runs spanning three technology nodes: ASAP7, NanGate45, and Sky130HD. From these layouts, we extract 61,855 3D windows across three size tiers to enable transfer learning and scalability studies. High-fidelity capacitance labels are generated using RWCap, a state-of-the-art random-walk solver, and validated against the industry-standard Raphael, achieving a mean absolute error of 0.64% for total capacitance. Each window is pre-processed into density maps, graph representations, and point clouds. We evaluate 10 machine learning architectures that illustrate dataset usage and serve as baselines, including convolutional neural networks (CNNs), point cloud transformers, and graph neural networks (GNNs). CNNs demonstrate the lowest errors (1.75%), while GNNs are up to 41.4x faster but exhibit larger errors (10.2%), illustrating a clear accuracy-speed trade-off. Code and dataset are available at https://github.com/THU-numbda/CapBench.

• The paper introduces CapBench, a high-fidelity multi-PDK dataset that improves ML-based post-layout capacitance extraction with sub-1% error using RWCap.
• It details multi-modal data representations—3D density maps, point clouds, and graphs—and benchmarks CNNs, GNNs, and point cloud transformers against traditional methods.
• The dataset enforces rigorous train/test de-duplication and reproducible benchmarking, setting a new standard for open EDA ML research.

CapBench: A Multi-PDK Dataset for Machine-Learning-Based Post-Layout Capacitance Extraction

Introduction and Motivation

The paper "CapBench: A Multi-PDK Dataset for Machine-Learning-Based Post-Layout Capacitance Extraction" (2604.11202) introduces CapBench, an open, high-fidelity dataset targeting the critical task of 3D interconnect capacitance extraction across multiple process technology nodes. Recognizing that traditional field-solver-based extraction is computationally expensive and that the lack of open, high-quality datasets impedes the adoption and benchmarking of ML methods in electronic design automation (EDA), CapBench addresses a fundamental bottleneck for ML-driven physical verification. The dataset is derived from open-source designs, routed using OpenROAD across ASAP7, Nangate45, and Sky130HD PDKs, and labeled with the RWCap random walk field solver, thoroughly benchmarked against the industry standard Raphael.

Dataset Generation and Methodological Rigor

CapBench systematically constructs its corpus by synthesizing, placing, and routing a selection of representative designs—including CPUs and SoCs—across multiple nodes using the fully open-source OpenROAD flow. This process (Figure 1) creates layout snapshots at various physical scales by tiling each chip into non-overlapping windows; critical post-processing with KLayout ensures spatial de-duplication to eliminate label leakage between train and test splits.

Figure 1: CapBench dataset generation flow and toolchain.

Each extracted window encapsulates a 3D conductor geometry, represented as multi-layer density maps, spatial graphs, and point clouds. This supports both direct adoption by vision-based and geometric deep learning methods and enables rigorous cross-architecture comparison. The underlying designs span diverse microarchitectural characteristics, ranging from control-centric RISC cores (Ibex, TinyRocket) to high-bandwidth, pipelined workloads (JPEG, CVA6, Chipyard), and are placed and routed in all three supported PDKs. Window generation is carefully balanced via margin and size policies (Figure 2), ensuring comprehensive area coverage while preventing design rule violations at the edges of windows.

Figure 2: Window placement on a 2$\times$2 grid.

Capacitance labels are computed using the stochastic field-solver RWCap, with stringent convergence criteria (variance <0.5%) and systematic validation against Raphael. Benchmarking in the paper demonstrates that RWCap achieves sub-1% mean absolute error for total capacitance and $\sim$2% for coupling, while delivering 2–3 orders of magnitude speedup relative to Raphael. OpenRCX, in contrast, yields $\sim$20% error using pattern-matching decks, confirming that CapBench’s use of RWCap yields a step-function advance in label fidelity (Figure 3).

Figure 3: RWCap and OpenRCX errors with Raphael as the reference. (a) RWCap, (b) OpenRCX.

Dataset Structure and Multi-Representation Support

Each window in CapBench is released in three canonical formats:

• 3D Density Maps: Optimized for image-based models, with per-pixel occupation values per metal/via layer.
• Point Clouds: Surface-sampled, spatially encoded, and ready for transformer architectures.
• Graphs: Nodes represent cuboid conductor fragments; edges encode spatial and long-range coupling priors, supporting high-throughput batch GNN inference.

This multi-representation approach ensures that CapBench benchmarks are representative and supports fair, exhaustive architectural exploration. Figure 4 illustrates the flow for GNN-based total capacitance prediction, leveraging cuboid decomposition, graph construction, message-passing, and attention-based pooling to yield net-level capacitance values.

Figure 4: GNN total capacitance prediction flow for a window with two conductors.

Baseline ML Architectures and Experimental Results

The paper implements and evaluates three dominant ML architecture families for capacitance prediction:

• CNNs (ResNet-34/50/101): Operating on multi-channel density maps, these provide the highest accuracy (MAPE down to 1.75%) but are computationally heavier.
• Point Cloud Transformers (PCTs): Flexible, small-parameter models (1.85–3.03M params) with accuracy (MAPE $\sim$6.78–8.75%) depending strongly on point resolution and window size.
• GNNs (GCN, GAT, GATv2): Exploiting conductor graph structure, GNNs achieve the highest throughput (up to 41.4x faster per window than ResNet-34), but at a cost of larger error (MAPE 10.2–21.4%).

A key finding is the explicit and measured accuracy–throughput trade-off. For instance, while CNNs exhibit the lowest error across all nodes, GNNs scale much more efficiently to many-window inference scenarios. The results also systematically document the effect of architectural capacity (depth, parameter count) on both speed and accuracy metrics.

Label Quality and Baseline Benchmarking

The most robust aspect of CapBench is its label verification and reproducibility ethos. RWCap-labeled capacitances, compared across thousands of windows with Raphael, consistently yield mean absolute total capacitance errors less than 1%. OpenRCX, the de facto open-source parasitic extractor, exhibits an order of magnitude worse accuracy, especially when evaluated on novel geometries and non-patterned layouts present in CapBench.

Additionally, all baselines are released with both code and evaluation pipelines, enabling exact reproduction of results and rapid benchmarking of novel architectures. The dataset supports transfer learning and scalability analyses due to its stratified design/PDK/window structure.

Theoretical and Practical Implications

CapBench facilitates rigorous benchmarking of ML architectures for parasitic extraction, a key post-layout EDA task. By enabling deep and broad learning-based exploration over diverse PDKs and geometries and providing high-fidelity, reproducible ground truth, CapBench breaks a historic barrier to open ML-for-EDA research. The explicit modeling of speed–accuracy trade-offs demonstrates that CNN-based surrogates are technically competitive with field-solvers, while GNNs offer unprecedented throughput and scalability, suggesting new directions for in-place, on-the-fly parasitic analysis in large physical design flows.

On the theoretical side, CapBench’s rigorous train/test de-duplication pipeline and provision for heterogeneous representations make it a substrate for methodologically careful research into generalization, inductive bias, and transfer learning in IC layout analysis.

Future Directions

Future work enabled by CapBench includes the design of hybrid surrogate models blending the spatial precision of CNNs with the scalability of GNNs, and research into adaptive transfer learning across process nodes. The field can now properly benchmark cross-representation and cross-PDK generalization and tackle the exploration of uncertainty quantification and semi-supervised learning for physical verification tasks.

Conclusion

CapBench establishes a new standard for open, reliable, and high-fidelity datasets in EDA ML research by delivering multi-modal, rigorously validated, and fully reproducible capacitance extraction across the three most relevant open-source PDKs. The comprehensive baselines highlight clear pathways to improve both accuracy and throughput, and the full release of data, code, and evaluation scripts positions CapBench as a foundation for continued advances in data-driven physical design and verification.