Validate Fidelity-Concentration Behavior on Quantum Hardware

Determine whether the narrowing of the usable fidelity range with increasing register width observed in exact and simulated-noise experiments persists on quantum hardware that does not incur the same statevector simulation cost.

Background

The study evaluates fidelity-based quantum kernels and graph constructions primarily through exact statevector simulation, with additional simulated finite-shot and depolarising noise experiments. In the evaluated datasets, increasing the register width reduces the number of region pairs with sufficiently large fidelity, limiting the usable fidelity range for graph construction, while larger feature capacity would favor wider registers.

The authors note that actual hardware introduces hardware-specific effects, including gate-level noise and decoherence, and may alter the computational trade-off observed in simulation. Consequently, it remains unresolved whether the observed relationship between register width, fidelity concentration, and practical usability continues to hold on hardware that does not bear the same simulation cost.