Dynamic promotion threshold for NVPC’s NVM-side LRU

Develop a dynamic strategy for selecting the promotion threshold in NVPC’s NVM-extended page cache, which determines when pages with access counters are promoted from non-volatile memory (NVM) back to dynamic random-access memory (DRAM), replacing the current static threshold value of 4 while maintaining stable behavior without thrashing between DRAM and NVM.

Background

NVPC extends the Linux page cache across DRAM and NVM. Pages deemed cold in DRAM are demoted to NVM, where they are managed by an LRU augmented with per-page access counters. Pages whose counters exceed a promotion threshold are moved back to DRAM. This threshold can be either static or dynamic.

In the current prototype, the promotion threshold is fixed at 4 to mitigate thrashing between DRAM and NVM. The authors explicitly note that devising a dynamic strategy for this threshold is deferred, indicating an unresolved design decision that could improve adaptability across workloads.