Walking Cat Architecture

• Walking Cat Architecture is a fault-tolerant quantum computing blueprint that employs cat-state ancillas and LDPC codes to facilitate scalable quantum operations on trapped-ion platforms.
• It leverages innovative constructs such as cat factories, a walking cat protocol, and a 2D QCCD micro-architecture to enable fast, parallelizable logical measurements and T-gate executions.
• The design demonstrates practical applicability with benchmarks in Hamiltonian simulation and Shor’s algorithm, highlighting trade-offs in code overhead, throughput, and micro-architectural complexity.

The Walking Cat architecture defines a comprehensive and practical fault-tolerant quantum computing blueprint for trapped-ion platforms, integrating cat-state-based logical measurements, LDPC code-based quantum error correction, a 2D QCCD micro-architecture, fast streaming decoders, and hierarchical compilation. The architecture is characterized by its use of “cat factories”—dedicated regions producing large entangled cat states as key ancillas—and its compatibility with experimentally demonstrated hardware elements. The approach emphasizes high-throughput, parallelizable operations, and scalability, with configurations enabling hundreds of logical qubits and execution of millions of $T$ gates per day using only thousands of physical qubits (Tripier et al., 21 Apr 2026).

1. Cat States and the Walking Cat Protocol

At its core, the Walking Cat architecture employs cat states—$w$-qubit GHZ-type entangled states $$|\mathrm{CAT}_w\rangle = (|0\rangle^{\otimes w} + |1\rangle^{\otimes w})/\sqrt{2}$$ —as ancillas for fault-tolerantly measuring multi-qubit Pauli operators $\overline{P} = \prod_{i=1}^w P_i$. Logical measurements proceed via (a) entangling each $P_i$-rotated data qubit with a cat ancilla qubit (using CNOT/CZ), (b) measuring all cat qubits in the $X$ basis, and (c) evaluating the parity of measurement outcomes.

Cat factories produce cat states via a doubling-tree CNOT circuit in $\lceil \log_2 w \rceil + 1$ rounds, followed by $m$ rounds of $ZZ$-check verification with ancillas. Only cat states passing all checks (rejection probability $\sim (2m+1)\,w\,p$ for $w$0 the gate error rate) are distributed for consumption.

The "walking cat" protocol shuttles verified cat qubits under target memory/data blocks along QCCD junctions, merges them for logical measurements, and returns them for possible reuse. For inter-block measurements, two cat states are stitched using Bell pairs generated in Bell factories.

2. Quantum LDPC Codes and Error Model

Logical qubits are encoded in quantum LDPC codes with parameters:

• [[70, 6, 9]]: 6 logical qubits, distance 9, code rate $w$1
• [[102, 22, 9]]: 22 logical qubits, distance 9, code rate $w$2

A standard circuit-level noise scaling for code distance $w$3 models the logical error per operation as

$w$4

with $w$5 the two-qubit physical error rate, $w$6 the code threshold, and $w$7. At $w$8, one finds $w$9–$$|\mathrm{CAT}_w\rangle = (|0\rangle^{\otimes w} + |1\rangle^{\otimes w})/\sqrt{2}$$0.

3. Fault-Tolerance Protocols

Syndrome Extraction

The three-ring framework arranges data and ancilla qubits in concentric rings on the 2D QCCD array. Ancillas undergo cyclic shifts along three nested “loops” (short, medium, long) to enact stabilizer CNOTs without all-to-all ion connectivity. Each syndrome-extraction cycle (SEC) combines parallel CNOTs and ancilla shuttling, requiring $$|\mathrm{CAT}_w\rangle = (|0\rangle^{\otimes w} + |1\rangle^{\otimes w})/\sqrt{2}$$1 physical-operation cycles (POCs), $$|\mathrm{CAT}_w\rangle = (|0\rangle^{\otimes w} + |1\rangle^{\otimes w})/\sqrt{2}$$2s each, yielding a SEC time of approximately $$|\mathrm{CAT}_w\rangle = (|0\rangle^{\otimes w} + |1\rangle^{\otimes w})/\sqrt{2}$$3ms.

Decoding

A streaming beam search decoder converts syndrome bits $$|\mathrm{CAT}_w\rangle = (|0\rangle^{\otimes w} + |1\rangle^{\otimes w})/\sqrt{2}$$4 to detector outcomes $$|\mathrm{CAT}_w\rangle = (|0\rangle^{\otimes w} + |1\rangle^{\otimes w})/\sqrt{2}$$5, rendering the parity-check matrix into a banded staircase form. Using a sliding-window (window size $$|\mathrm{CAT}_w\rangle = (|0\rangle^{\otimes w} + |1\rangle^{\otimes w})/\sqrt{2}$$6, commit size $$|\mathrm{CAT}_w\rangle = (|0\rangle^{\otimes w} + |1\rangle^{\otimes w})/\sqrt{2}$$7), the inner decoder tackles $$|\mathrm{CAT}_w\rangle = (|0\rangle^{\otimes w} + |1\rangle^{\otimes w})/\sqrt{2}$$8 block subproblems and commits corrections for three SECs at a time. The achieved logical error rate is within $$|\mathrm{CAT}_w\rangle = (|0\rangle^{\otimes w} + |1\rangle^{\otimes w})/\sqrt{2}$$9 of an optimal global decoder, down to $\overline{P} = \prod_{i=1}^w P_i$0. Latency per SEC is approximately $\overline{P} = \prod_{i=1}^w P_i$1ms (Q70), $\overline{P} = \prod_{i=1}^w P_i$2ms (Q102); the 99\%-tile reaction time is $\overline{P} = \prod_{i=1}^w P_i$3ms (Q70), $\overline{P} = \prod_{i=1}^w P_i$4ms (Q102).

Clifford-Frame Tracking

Logical Pauli measurements and Clifford gates are implemented by updating a Clifford-frame matrix $\overline{P} = \prod_{i=1}^w P_i$5 for each block and by measuring appropriate conjugated operators. This Pauli-by-measurement/Clifford-by-frame scheme requires no physical Pauli/Clifford gates.

4. Micro-Architecture and Parallelism

The underlying hardware comprises a 2D QCCD chip, partitioned into:

• “Gate” rows for one- and two-qubit RF gates
• “Optical” rows for measurement/reset
• Ion transport junctions for shuttling

Memory blocks organize data, ancilla, and beacon rows in a folded three-ring structure, with each block containing $\overline{P} = \prod_{i=1}^w P_i$6 qubits plus ten-qubit reservoirs. Cat factories possess four rows of $\overline{P} = \prod_{i=1}^w P_i$7 wells for in-place cat state preparation and verification.

Movement strategies include block-swapping (long-ring), cyclic translation of ancillas (medium-ring), and intra-row permutations (short-ring). RF antennas beneath all gate rows enable billion-scale single/two-qubit gate parallelism. Measurement/reset operations in optical rows are pipelined with shuttling.

Cat-state routing involves shuttling batches of $\overline{P} = \prod_{i=1}^w P_i$8 qubits under target blocks via vertical injection, accordion-like horizontal transport, and merging. The routing cost for $\overline{P} = \prod_{i=1}^w P_i$9, $P_i$0 is $P_i$1 POC.

5. Compilation, Decoding, and Resource Estimates

A hierarchical compiler (Qualtran/QREF style) expands algorithmic specifications to logical instructions—Pauli preparations, logical measurements (LM1, LM2), frame-tracked Cliffords, and magic-state injections. Magic-state injection/verification employs IS+H primitives (logical $P_i$2 via cat-based $P_i$3 measurement).

The decoder operates continuously during SECs, delivering logical outcomes with $P_i$4 ms latency.

Representative resource estimates include:

Instance	Memory Code	Magic Factory Code	Logical Qubits	Physical Qubits
Dense	$P_i$5 [[102,22,9]]	$P_i$6CH₂ [[54,2,10]]	110	2,514

Throughput for $P_i$7-gates (double $P_i$8 via paired $P_i$9 states) is $X$0 ms latency, yielding $X$1 $X$2-gates/s ($X$3/day). One million $X$4-gates/day is supported with $X$5–$X$6 physical qubits.

6. Application Benchmarks and Performance

The architecture supports quantum simulations and factoring tasks with practical runtimes:

• Hamiltonian simulation (100-site Heisenberg model, degree 7): Sixth-order Trotter with 10 steps ($X$7 2nd-order steps, $X$8 sequential $X$9QZ layers plus controlled-phase estimation). Using $\lceil \log_2 w \rceil + 1$0 physical qubits:
  • 80 sites: $\lceil \log_2 w \rceil + 1$110 hours
  • 100 sites: $\lceil \log_2 w \rceil + 1$218 hours
  • 120 sites: $\lceil \log_2 w \rceil + 1$353 hours
  • Aggregate time for iterative QPE (50 shots): $\lceil \log_2 w \rceil + 1$4 month
• Shor’s algorithm: Factoring a 30-bit integer (1,071,514,531) requires 34 Q70 and 9 CH₂ codes, runtime $\lceil \log_2 w \rceil + 1$5 day. 10/20/40-bit instances require $\lceil \log_2 w \rceil + 1$61 hour to 2 days, respectively.

Simulation results at $\lceil \log_2 w \rceil + 1$7, leakage $\lceil \log_2 w \rceil + 1$8, and loss $\lceil \log_2 w \rceil + 1$9 yield logical errors per SEC of $m$0 (Q70) and $m$1 (Q102).

Magic-state factories:

• CH₂ in $m$2-injections, weight-54 Viterbi check" title="" rel="nofollow" data-turbo="false" class="assistant-link">[54,2,10]: rejection $m$3\%, output error $m$4, average $m$5 SEC/attempt.
• MEK in $m$6-injections, 3 Viterbi checks" title="" rel="nofollow" data-turbo="false" class="assistant-link">[70,6,9]: rejection $m$7\%, output error $m$8, average $m$9 SEC/attempt.

7. Architectural Variants and Trade-Offs

Three principal architectural realizations are distinguished:

• Simple: single [[70,6,9]] code for both memory and magic state distillation; minimal code diversity but higher magic factory overhead and reduced throughput
• Fast: magic-state distillation using CH₂ in [[54,2,10]], memory in [[70,6,9]], and $ZZ$0–frame tracking for optimal $ZZ$1 throughput
• Dense: memory using [[102,22,9]] for maximal logical qubits per physical qubit

Trade-offs relate primarily to code overhead, throughput, and micro-architectural complexity. The architecture demonstrates that hundreds of logical qubits and millions of logical gates per day are attainable with near-term trapped-ion hardware, enabling classically intractable simulations and practical Shor’s algorithm execution (Tripier et al., 21 Apr 2026).