VeriDFT: RTL DFT Repair Dataset

• VeriDFT is a curated dataset of 437 Verilog RTL pairs, each containing a single DFT violation corrected to ensure synthesizability and logical equivalence.
• It employs TF-IDF vectorization combined with neural encoding and contrastive learning to enable retrieval-augmented repair in the VeriRAG framework.
• The dataset's rigorous curation and verification, including synthesis with Xcelium and equivalence checking with Conformal LEC, ensure compliance with specific DFT error types.

Searching arXiv for papers on VeriDFT and related terms to ground the article. VeriDFT is a Verilog-based Design for Testability (DFT) dataset curated for DFT-aware RTL repairs and introduced alongside the retrieval-augmented framework VeriRAG, described as the first LLM-assisted DFT-EDA framework (Qi et al., 21 Jul 2025). It is organized as a collection of faulty and corrected Verilog-RTL pairs intended to support automated repair of DFT violations while preserving synthesizability and logical equivalence. In formal terms, each example consists of an original RTL design $v_i$, a corrected RTL design $v_i'$, a JSON-derived vector representation $x_i\in\mathbb{R}^{M}$, and a one-hot DFT label $y_i\in\{0,1\}^4$, with the full dataset given by

$$\text{VeriDFT}=\Bigl\{\bigl(v_i,\,v_i',\,x_i,\,y_i\bigr)\Bigr\}_{i=1}^{N},$$

where $N=437$.

1. Definition and representational structure

VeriDFT is defined as a finite collection of Verilog-RTL examples in which each original design exhibits exactly one DFT violation of interest, and each corrected design is manually edited so that it compiles, is free of the original DFT violation, and is logically equivalent to the faulty source as verified by Conformal LEC (Qi et al., 21 Jul 2025). The four DFT error types are ACNCPI, CLKNPI, CDFDAT, and FFCKNP.

The dataset associates each RTL example with a JSON representation obtained via Yosys netlist-to-JSON conversion followed by TF-IDF vectorization. The corresponding label is a one-hot encoding over the four violation classes $$\{\text{ACNCPI},\text{CLKNPI},\text{CDFDAT},\text{FFCKNP}\}$$. During retrieval in VeriRAG, only the tuples $\bigl(x_i,y_i,v_i'\bigr)$ are used as reference “answer” units. This suggests that VeriDFT is not merely a benchmark corpus but a retrieval substrate designed to support structure-matched repair.

A central restriction is that each retained faulty RTL file contains exactly one DFT violation type. The curation criteria therefore define VeriDFT as a single-error repair dataset rather than a general corpus of arbitrary RTL defects.

2. Construction pipeline and curation criteria

VeriDFT was built on top of an open-source GitDataset of 108 971 Verilog files (Qi et al., 21 Jul 2025). The construction pipeline first filtered out non-circuit files, including testbenches, wrappers, and files without any core RTL logic. It then bypassed missing IP cores by patching designs that instantiated proprietary IPs, such as Xilinx BRAM, through insertion of empty-module stubs with matching port lists so that synthesis could proceed.

The remaining files were compiled with Cadence Xcelium via HAL, with the compiler’s DFT checker configured to report only four violations: ACNCPI, defined as asynchronous set/reset not driven by a primary input; CLKNPI, defined as an internal clock net not derived from primary inputs; CDFDAT, defined as a clock used as a data signal; and FFCKNP, defined as a flip-flop output driving a clock domain. Files showing zero or more than one DFT violation type were discarded, and files that still failed synthesis were removed.

After this filtering, 437 Verilog files remained, each annotated with exactly one of the four DFT error types. Engineers then manually edited each file to produce a DFT-compliant version. Each correction was verified by Xcelium for successful compilation and absence of DFT errors, and then checked for logical equivalence by Cadence Conformal LEC. The resulting curation standard tightly couples DFT compliance with synthesizability and equivalence preservation.

3. Corpus composition and split design

The 437 examples are partitioned into training, reference, and test subsets with distinct roles in the VeriRAG workflow (Qi et al., 21 Jul 2025).

Split	Files	Purpose
Training	85	Train the autoencoder with contrastive learning
Reference	35	Fixed library of (faulty + corrected) pairs for retrieval in test time
Test	317	Evaluate VeriRAG’s end-to-end repair performance

The split proportions are 19.4% training, 8.0% reference, and 72.6% test. The training subset is therefore relatively small and specialized, while the test subset dominates the corpus. This suggests an evaluation regime centered on retrieval-guided generalization rather than large-scale supervised fitting.

The error-type distribution across all 437 examples is approximately 22% ACNCPI, 28% CLKNPI, 25% CDFDAT, and 25% FFCKNP. Code-length histograms show most files between 30 and 150 lines of RTL. Taken together, these properties indicate a compact but curated repair dataset with moderate class balance across four DFT-specific error families.

4. Feature extraction, embedding, and similarity measurement

For similarity modeling, each Yosys-generated JSON netlist is tokenized and vectorized into $\mathbf{x}\in\mathbb{R}^{512}$ via scikit-learn’s TF-IDF with smoothing and sublinear scaling (Qi et al., 21 Jul 2025). On top of this representation, the framework jointly trains an encoder $f:\mathbb{R}^{512}\to\mathbb{R}^{128}$, a decoder $v_i'$0, and a DFT-type classifier $v_i'$1 on the 85-file training split.

The learning objective combines reconstruction, classification, and contrastive terms. For a mini-batch $v_i'$2, the reconstruction loss is

$v_i'$3

and the classification loss is

$v_i'$4

A contrastive loss with margin $v_i'$5 is applied on normalized embeddings, and the overall loss is

$v_i'$6

At retrieval time, the similarity score between a test embedding $v_i'$7 and a reference embedding $v_i'$8 is the cosine similarity

$v_i'$9

and the retrieved example is $x_i\in\mathbb{R}^{M}$0. The architecture therefore ties dataset design, metric learning, and in-context example selection into a single retrieval pipeline.

5. Integration into the VeriRAG repair workflow

Within VeriRAG, VeriDFT functions as the reference library for retrieval-augmented DFT correction (Qi et al., 21 Jul 2025). For each faulty design $x_i\in\mathbb{R}^{M}$1, the pipeline converts the Verilog source to its JSON representation $x_i\in\mathbb{R}^{M}$2 using Yosys, embeds it through the trained encoder, retrieves the most similar reference example by cosine similarity, and constructs a multipart LLM prompt. That prompt contains a general task description for DFT compliance, formal definitions of the four error types, the retrieved faulty↔corrected pair $x_i\in\mathbb{R}^{M}$3 as an in-context example, and the target faulty design $x_i\in\mathbb{R}^{M}$4.

Repair proceeds iteratively for up to $x_i\in\mathbb{R}^{M}$5 rounds. In each round, the LLM generates a candidate repair, the candidate is synthesized with Xcelium, and any compiler or DFT error messages are fed back into the next prompt if errors remain. Finalization occurs only when a candidate passes synthesis with zero DFT errors, after which Conformal LEC is run against the original faulty design to ensure logical equivalence.

Using VeriRAG with VeriDFT yields fully automated DFT correction and a 7.72-fold improvement in successful repair rate compared to the zero-shot baseline; the supplied example reports an increase from 6.96% to 53.76% on GPT-o1. Ablation studies are reported to confirm the contribution of each component of the VeriRAG framework. The data, models, and scripts are open-sourced at the repository identified in the paper.

6. Representative violation patterns and scope boundaries

The supplied examples illustrate how VeriDFT operationalizes DFT repair at the RTL level (Qi et al., 21 Jul 2025). For ACNCPI, the faulty design uses an internally generated asynchronous control, such as internal_set, in an always @(posedge clk or posedge internal_set) block. The correction exposes that signal as a primary input so that the DFT tool can control it during scan. For CLKNPI, the faulty pattern derives a downstream clock from internal logic, such as cnt[1] from a divider, and the correction avoids using that derived signal as a direct clock; instead, downstream flops are driven from the primary clock and the example inserts a proper clock-gating cell through a cgate_cell instance. Analogous small-scale examples are stated to exist for CDFDAT and FFCKNP.

These examples delimit the intended scope of the dataset. VeriDFT is specialized to DFT-aware repairs that preserve logical behavior, not to arbitrary functional bug fixing, broad refactoring, or unrestricted RTL optimization. The requirement that each example contain exactly one of four DFT violation types and a rigorously validated correction reinforces that specialization.

A distinct usage of the string “VeriDFT” appears in the supplied material for a step-by-step account of verifying the variance of the DFT-based randomness test using Parseval’s theorem (Iwasaki, 2018). In that separate context, the derivation assumes a constant-energy sphere model, studies the statistic $x_i\in\mathbb{R}^{M}$6, and yields the large-$x_i\in\mathbb{R}^{M}$7 approximation

$x_i\in\mathbb{R}^{M}$8

That usage is distinct from the Verilog dataset introduced in VeriRAG and does not alter the meaning of VeriDFT within DFT-aware RTL repair.