Unified Processing Elements (UPEs)

• Unified Processing Elements (UPEs) are programmable logic blocks designed for scalable, parallel processing in heterogeneous computing pipelines.
• They consolidate diverse low-level operators into a reconfigurable unit for tasks like edge sorting, deduplication, and graph preprocessing on FPGAs.
• By leveraging spatial parallelism and pipelined processing, UPEs achieve significant speedups, outperforming traditional CPU and GPU methods.

Unified Processing Elements (UPEs) are programmable logic blocks designed for scalable, parallel data transformation and aggregation in heterogeneous computing pipelines, especially FPGAs. UPEs subsume diverse low-level operators (e.g., comparators, partition sorters, uniqueness filters, prefix sum/scatter) into a single reconfigurable unit that can efficiently process a range of sequence-based tasks, such as edge sorting and unique vertex selection, in hardware-accelerated preprocessing. Their design allows full exploitation of spatial parallelism and pipelined processing and is central to state-of-the-art graph preprocessing accelerators.

1. Conceptual Foundation and Design Principles

UPEs are architected as composable, highly parallel hardware modules organized to execute multi-stage, data-centric workloads. Each UPE instantiates a configurable logic kernel capable of implementing algorithms such as radix sort, set-partitioning, prefix sum, unique-removal, and selection, all of which are critical to memory-bound and irregular data preprocessing. UPEs are tightly integrated with buffer controllers and frequently pipelined, employing dynamically switchable datapaths for different operation modes (Kang et al., 31 Jan 2026).

A key design principle is the decoupling of the UPE's logic from input/output bandwidth bottlenecks. By leveraging wide, synchronous register arrays and local scratchpads, UPEs sidestep the performance penalties typical of serial execution and contention for shared resources on CPUs/GPUs. The unit is often designed for parameterized "chunk" sizes (e.g., 128 elements per cycle) so that array-type operations can fully exploit FPGA LUT and BRAM resources.

2. Dataflow Integration and Processing Roles

UPEs operate within multi-stage preprocessing pipelines, such as AutoGNN, where they alternate and interlock with specialized reduction components like Single-Cycle Reducers (SCRs). The canonical dataflow pattern includes:

1. Edge Ordering: UPEs perform streaming, high-throughput sorting (e.g., radix sort) on edge lists—specifically, the "coordinate list" (COO) format, crucial for transforming graphs into compressed, index formats (CSC/CSR).
2. Unique Vertex Selection and Sampling: For neighborhood sampling in GNN applications, UPEs partition sorted edges, deduplicate vertices, or select $k$-sized random neighbor subsets using set-partitioning and prefix sum/scatter circuits.
3. Connectivity and Index Construction: After sequencing, UPEs prepare the index and pointer arrays needed by subsequent SCR units for rapid renumbering and layout.

The composition of these stages allows pipelines to reorder, sample, and deduplicate in situ without round-trips to DRAM or excessive serialization (Kang et al., 31 Jan 2026).

3. Microarchitectural Structure

A UPE comprises a parallel comparator array linked with custom logic (e.g., a multi-input adder tree, bitfield, or priority multiplexer) and can be programmed to change its logical function between pipeline stages. For example, when operating as a sorter, the array is configured to partition elements by radix digit or threshold, iteratively converging each chunk to sorted order. For unique selection, comparators and movers identify boundaries and write out only new values.

This reconfigurability is supported by local configuration registers and handshaking with a user-level controller or host software, which profiles the input workload and selects optimal parameters (e.g., chunk size, sort radix, operator mode). UPE resource allocations in FPGA designs may consume up to 70% of LUT resources in some pipeline floorplans, underscoring their centrality to throughput optimization (Kang et al., 31 Jan 2026).

4. Interaction with Specialized Reducers and Pipeline Scheduling

UPEs form one half of a tightly coupled dual-element hardware stack, with SCRs handling global, associative reductions that are difficult to parallelize by conventional means. The typical pattern is:

• UPE Stage: Performs bulk, parallel sorting, deduplication, or partitioning of a data block.
• SCR Stage: Executes constant-time, segment-wide operations—such as counting (pointer array construction) or mapping (renumbering for sampled subgraphs)—that require global aggregation.

This staging is scheduled by a lightweight controller that dynamically alternates between UPE-driven and SCR-driven pipeline blocks. The controller maintains counters, configures operand widths, and coordinates memory access across the pipeline.

5. Quantitative Performance Characteristics

The integration of UPEs allows for orders-of-magnitude increases in throughput compared to CPU or GPU systems. For example, in the AutoGNN system, the majority of the FPGA floorplan is dedicated to UPEs, yielding aggregate throughput proportional to the chunk width and number of concurrent units. For sorted edge lists or partitioned vertex sets, UPEs can process hundreds to thousands of elements per cycle at peak.

Combined with SCRs, UPEs achieve up to $9.0\times$ speedup over CPU-based and $2.1\times$ over GPU-based preprocessing for end-to-end GNN workload pipelines, with measured memory-bandwidth utilization of over 91% for large graphs compared to below 31% for best-in-class GPU implementations (Kang et al., 31 Jan 2026).

6. Architectural and Research Significance

UPEs exemplify the move toward domain-specialized, programmable hardware elements for data-intensive preprocessing, especially for irregular, non-numeric workloads seen in real-world graphs. Their core attributes—reconfigurability, tight spatial integration, and high parallelism—reflect a convergence of hardware design principles from SIMD-style ALUs, streaming dataflow architectures, and pattern-specific accelerators.

A plausible implication is that further development of UPE-style architectures could extend to broader classes of symbolic computation, domain-specific language execution, and preprocessing for mixed-tabular, natural language, or temporal data. The embedding of UPEs in dynamically adaptive FPGA workflows suggests a direction for future heterogeneous compute platforms highly optimized for both high arithmetic intensity and complex data mediation (Kang et al., 31 Jan 2026).