TypedSchematics: Typed PCB Design Tool

• TypedSchematics is a block-based PCB design tool that uses a typed annotation language to validate connections and ensure component compatibility.
• It integrates a visual schematic model called Mats for real-time error detection, reducing wiring errors and simplifying circuit assembly.
• Its automated merging pipeline and community-driven library enable rapid PCB synthesis and manufacturable designs without third-party assistance.

TypedSchematics is a block-based standalone PCB design tool for printed circuit board design that supports beginners create their own PCBs by providing a language syntax for typing circuit blocks with circuit data that addresses multiple challenges, from real-time detection of connection errors to automated composition and user-scalable libraries of circuit blocks (Garza et al., 18 Sep 2025). It is presented against the background that, within PCB design, the reuse of circuit design blocks is a major preventing factor inhibiting beginners from reusing designs made by experts, a common practice in software but non-existent in circuit design at large, and that existing efforts such as SparkFun ALC and Altium Upverter lack merging techniques that safely guide users in connecting different circuit blocks without requiring assistance from third-party engineers (Garza et al., 18 Sep 2025). The system combines a typed annotation language, a visual schematic model called Mats, automated schematic and PCB merging, and an extensible block library, with evaluation centered on design correctness, time to complete, user confidence, and preference (Garza et al., 18 Sep 2025).

1. Problem setting and design objectives

TypedSchematics is motivated by a specific barrier in beginner-oriented PCB design: block reuse exists as a goal, but safe composition of blocks is not adequately supported in mainstream tooling. The central claim is not merely that blocks can be reused, but that they can be reused under explicit circuit-interface typing, immediate validation, and automated synthesis of a full schematic and PCB layout (Garza et al., 18 Sep 2025).

The tool is described as providing three capabilities that commercial block-based tools do not jointly provide: immediate, in-tool error validation, automatic PCB synthesis, and a user-extendable library of circuit blocks (Garza et al., 18 Sep 2025). Its intended role is therefore intermediate between a conventional schematic editor and a curated module marketplace. Rather than requiring novices to infer compatibility from datasheets or naming conventions, it externalizes compatibility in typed circuit metadata and validates the user’s composition directly in the design interface (Garza et al., 18 Sep 2025).

The implementation details describe a web-based frontend, while the paper’s abstract characterizes the system as a block-based standalone PCB design tool (Garza et al., 18 Sep 2025). Taken together, these descriptions indicate an architectural emphasis on an integrated environment rather than a plugin layered onto an existing editor. The broader objective is to lower the PCB design skill-floor while keeping the resulting designs manufacturable, including automatic generation of Gerber files for manufacturing (Garza et al., 18 Sep 2025).

2. Type language for circuit blocks

A defining feature of TypedSchematics is a minimal, symbolic language for annotating schematic blocks with type information directly in net or signal names, using existing PCB tools like Fusion 360 (Garza et al., 18 Sep 2025). The paper organizes these annotations into three categories: protocol circuit interface types, power circuit interface types, and global attributes (Garza et al., 18 Sep 2025).

Protocol circuit interface types use the syntax #Protocol.Signal_Voltage, with examples such as #[I2C](https://www.emergentmind.com/topics/individually-inferred-communication-i2c).SDA and #[SPI](https://www.emergentmind.com/topics/single-pixel-imaging-spi).MOSI (Garza et al., 18 Sep 2025). The language supports grouping through dot notation, alternate names through -, and optional connections through !, with #GPIO-RESET! given as an example of an optional GPIO named RESET (Garza et al., 18 Sep 2025).

Power circuit interface types use forms such as @VIN_Voltage, @VOUT_Voltage, and GND, with examples including @VIN_5V, @VOUT_3V-5V, and GND (Garza et al., 18 Sep 2025). These declarations express input and output voltages, including ranges, together with systematic ground assignment (Garza et al., 18 Sep 2025).

Global attributes use the syntax #{ ... } in relaxed JSON format, embedded as schematic comments or text (Garza et al., 18 Sep 2025). These store metadata such as block class—Power, Regulator, Peripheral, or Compute—and protocol-specific features such as I2C address or SPI master/slave status (Garza et al., 18 Sep 2025).

The significance of this language lies in how it turns informal naming conventions into typed interfaces usable by automated checks and composition logic. The paper also states that the language is easily extensible by adding new protocol/interface declarations and associated checks, implemented as JS modules (Garza et al., 18 Sep 2025). This makes the type system not only descriptive but operational: the same annotations drive compatibility checking, composition, and library extensibility.

3. Mats and real-time detection of connection errors

TypedSchematics uses a visual and interactive schematic representation called Mats, introduced to simplify the design process, reduce repetitive connections, reduce visual clutter and interaction cost, and facilitate real-time type checking (Garza et al., 18 Sep 2025). Mats is therefore not only a user-interface device but also the execution context for the tool’s validation logic.

The representation has a dual graph structure. Mat blocks—power and regulators—are organized in a tree structure, and each mat provides power/ground to all blocks sitting on it (Garza et al., 18 Sep 2025). General blocks—compute modules and peripherals—form a regular, flexible graph with multiple possible interconnections (Garza et al., 18 Sep 2025). Dragging a block onto a mat automatically connects its power/ground to the parent mat, eliminating manual voltage connections (Garza et al., 18 Sep 2025). The paper explicitly presents this as a way to avoid repeated VCC/GND wiring and the wiring spaghetti common in traditional schematic editors (Garza et al., 18 Sep 2025).

Validation is performed using a flow-based programming paradigm: as the user connects blocks, Mats passes messages, meaning type information, through the graph, triggering validation at each step, and error feedback is immediate in the GUI (Garza et al., 18 Sep 2025). Four main error types are checked (Garza et al., 18 Sep 2025):

• Protocol interface matching: wires must connect compatible protocol types, such as I2C to I2C (Garza et al., 18 Sep 2025).
• Voltage interface matching: blocks may only be joined if their voltage/capacity is compatible (Garza et al., 18 Sep 2025).
• Required/optional interface enforcement: mandatory protocol connections are enforced, excluding those marked optional with ! (Garza et al., 18 Sep 2025).
• Extended interface checks via global attributes: examples include I2C address conflict detection and ensuring only one master device for SPI (Garza et al., 18 Sep 2025).

The paper also enumerates more concrete detected conditions: voltage mismatches, incorrect protocol connection, missing required protocol connections, optional protocol lines left unconnected if allowed, address conflicts, hardware protocol violations such as multiple SPI masters, block-specific constraints from global attributes, and general ERC/DRC validation on imported and merged blocks (Garza et al., 18 Sep 2025). The technical significance is that these checks are integrated into interactive composition rather than deferred to post hoc review.

4. Automated composition, merging, and user-scalable libraries

Once the schematic is validated and PCB blocks positioned, TypedSchematics automatically synthesizes the full schematic and PCB layout, including generating Gerber files for manufacturing, by merging block files (Garza et al., 18 Sep 2025). The automated composition pipeline has both schematic-level and layout-level phases.

For schematic block merging, the system converts the Mats dual graph—mat and regular blocks—into a single graph and connects the signal nets as specified by the user’s typed schematic connections (Garza et al., 18 Sep 2025). For PCB block merging, layout files, currently Fusion 360, are merged, blocks are positioned, and traces between blocks are automatically routed using Fusion 360’s auto-routing in the backend (Garza et al., 18 Sep 2025). Duplicate references are handled by systematic renaming, and individual block origins are marked in the PCB silkscreen (Garza et al., 18 Sep 2025).

The design implementation described in the paper consists of a Python backend library called Swoop that manipulates schematic/layout files and triggers auto-routing in Fusion 360, together with a frontend using TypeScript, JS, HTML, Mats, Three.js, and Buërli for 3D PCB visualization (Garza et al., 18 Sep 2025). PCB block merging further includes unique-prefix renaming of reference designators and signal names, placement of PCB blocks with 3D preview, routing only the missing inter-block connections, white block borders added to PCB silkscreen to indicate block origin, and ERC and DRC pre- and post-merge to ensure integrity (Garza et al., 18 Sep 2025).

A separate design objective is user-scalable library growth. Any user can contribute new circuit blocks by annotating schematic blocks with the syntax language in Fusion 360, providing the corresponding PCB layout block and optional 3D STL model, and uploading these through the interface for validation, including ERC/DRC checks and type syntax validation (Garza et al., 18 Sep 2025). The paper states explicitly that no programming knowledge is required for block developers (Garza et al., 18 Sep 2025). This is important because it distinguishes TypedSchematics from vendor-curated block repositories: library growth is intended to come from community contribution rather than official module release cycles.

5. Evaluation and demonstrated use

The paper reports a user study with $n = 7$ university students with circuit design experience, comparing TypedSchematics with Fusion 360 on a thermostat-controller block-merging task using the same set of blocks and IO nets named clearly for fairness (Garza et al., 18 Sep 2025). The measured outcomes were design correctness, time to complete, user confidence, and preference (Garza et al., 18 Sep 2025).

Metric	TypedSchematics	Fusion 360
Schematic Design Errors	0/7 had errors	4/7 had errors
Design Time (schematic)	4.2 min (mean)	16.6 min (mean)
Design Time (PCB layout)	2.5 min (mean)	2.9 min (mean)
User Confidence	Mostly "Completely Confident"	Mostly "Somewhat/Fairly Confident"
Preference (schematic UI)	6/7 preferred Mats	1/7 preferred Fusion 360's
Ease of Learning	6/7 understood Mats’ logic fully after tutorial	—

The error breakdown reported for Fusion 360 was 4/7 had errors, with 3 power-related and 2 had signal errors (Garza et al., 18 Sep 2025). Qualitative feedback stated that TypedSchematics made participants “completely confident” and “very easy” to connect blocks, whereas Fusion 360 users struggled to identify required voltages/interfaces and sometimes resorted to datasheets and online searches (Garza et al., 18 Sep 2025).

Beyond the formal study, the paper cites three PCBs designed with TypedSchematics to showcase tool capabilities, including a blinky board, a thermostat, and a Wi-Fi mini-catamaran controller (Garza et al., 18 Sep 2025). One demonstration involved high school students: after a 15min intro, they designed a Wi-Fi motor controller PCB in 40min without help; the board was correctly manufactured and functioned as expected (Garza et al., 18 Sep 2025). The abstract frames this as demonstrating the potential of TypedSchematics to significantly lower the PCB design skill-floor (Garza et al., 18 Sep 2025).

6. Scope, limitations, and relation to typed schematic representations

TypedSchematics is presented as a beginner-support system, but the paper does not frame it as a complete replacement for professional PCB design environments. Its current support is limited to Fusion 360, only a few interface types—I2C, SPI, GPIO—no advanced features like analog/digital ground isolation or power/current constraint checking, and 2-layer boards only (Garza et al., 18 Sep 2025). Further development is identified as needed for interfaces like USB/HDMI and richer device blocks (Garza et al., 18 Sep 2025).

A common misconception would be that block-based design necessarily implies a closed ecosystem. The paper argues the opposite for TypedSchematics: any user can contribute new circuit blocks, and no programming knowledge is required for block developers (Garza et al., 18 Sep 2025). Another possible misconception is that simplification is achieved by suppressing electrical checks. In fact, the system’s central simplification strategy is typed validation and guided composition, including real-time error detection and pre- and post-merge ERC/DRC (Garza et al., 18 Sep 2025).

The tool also sits within a broader research trajectory toward typed and semantically explicit representations in PCB design. SchGen, for example, introduces a semantically grounded code representation that uses a typed, structured sequence of editing primitives, relative placement, and pin-name-based wiring for PCB schematic generation from natural-language requests (Luo et al., 28 May 2026). This suggests a broader convergence: typed representations can support either human-guided block composition, as in TypedSchematics, or model-guided schematic generation, as in SchGen. In both cases, the representation is used to expose functional intent more directly than geometry-heavy or purely textual schematic formats (Garza et al., 18 Sep 2025, Luo et al., 28 May 2026).