- The paper introduces SchGen, a semantic-grounded Python representation for generating editable PCB schematics, using relative placement and pin-name wiring to reduce LLM spatial and connectivity errors.
- SchGen fine-tunes a 20B-parameter model with LoRA on 2,105 schematics expanded to 8,420 training samples, achieving 82.0% valid circuits, 49.08 netlist Jaccard, and 60.5% expert-verified functional correctness.
- The results show representation choice matters more than model scale: SchGen outperforms prompted frontier models and generalizes to unseen designs, while still requiring human review and broader constraint and simulation support.
Overview
SchGen addresses the task of generating editable PCB schematics directly from natural-language user requests using a fine-tuned LLM (2605.30345). The authors identify two obstacles that have kept this problem unexplored relative to digital and analog IC generation: the absence of an LLM-suited schematic representation, and the absence of a paired prompt–schematic dataset. Their central claim is that representation design, rather than model scale, is the decisive factor: a 20B-parameter model trained on their semantic-grounded code representation outperforms frontier models such as GPT-5.2 and Grok-4 prompted with the same APIs, achieving 82% valid circuit rate and 60.5% expert-verified functional correctness versus 32% valid circuits for a raw KiCad file baseline.
Semantic-grounded code representation
The paper's core methodological contribution is a Python API layer that abstracts KiCad schematic editing into five primitives: add_schematic_symbol, add_label, get_pin_location, connect_pins, and write_out_all_wires. Two design choices convert geometry prediction into semantics-driven matching. First, symbol and label positions are expressed as offsets from anchor points (a functional center symbol for components, the attached pin for labels) rather than absolute coordinates, mitigating LLMs' known weakness in spatial reasoning over dozens of numerical coordinates. Second, wires are specified by connecting pins via symbolic names (e.g., VCC, TXD) rather than drawing wire segments at absolute coordinates.
The authors quantify learnability of three representation levels—Code-L1 (full proposal), Code-L2 (absolute coordinates), Code-L3 (absolute coordinates plus coordinate-based wires)—using Minimum Description Length, normalized Lempel–Ziv complexity, and validation loss. Code-L1 attains the lowest values on all three (MDL 2.19/2.31 mean/median; val loss 1.29/0.25 ×10⁻²), supporting the hypothesis that more compressible structure predicts better generalization. This is a proxy argument; the empirical confirmation comes from downstream generation results.
Dataset construction
Training data are produced by a human–agent pipeline applied to open-source designs from SparkFun under CC BY-SA 4.0. A multi-modal LLM (GPT-5) generates API-based code from design images, iterating against execution feedback until no errors or a maximum iteration count; human engineers then correct residual wiring mistakes. The paper reports that agentic sketching reproduces symbols within 5 iterations and requires under 20 seconds of verification per design, versus over 5 minutes to draw manually—a concrete efficiency claim, though it concedes that manual editing remains necessary because LLMs cannot reliably distinguish wire crossings from connections. A deterministic converter then parses KiCad s-expression files into pin/wire graphs and regenerates code in each representation level.
User requests are synthesized by multi-modal LLMs conditioned on exported images and netlists, seeded with human-authored examples, in two styles (concise and detailed). The final dataset contains 2105 schematics covering 1390 unique designs, expanded to 8420 samples via request styles and chain-of-thought distillation from GPT-oss-120B and GPT-oss-20B itself. Designs reach up to 39 symbols and 48 labels.
SchGen is obtained by supervised fine-tuning of Apache-2.0-licensed GPT-oss-20B with LoRA (rank 8, all-linear targets on MoE layers 7/15/23), requiring roughly 21 GPU-hours on a single A100—an unusually modest training budget for the reported gains.
Evaluation
Four metric families are used: valid circuits (executable code plus zero critical KiCad ERC errors), spatial violation (normalized bounding-box overlaps as a readability proxy), netlist accuracy (Jaccard/precision/recall over net sets), and expert verification by two annotators with cross-validation agreement within 3%. The authors justify omitting SPICE simulation because system-level mixed-domain PCB designs exceed available SPICE model coverage—a reasonable but notable limitation on functional validation rigor.
Representation ablations. Code-L1 dominates every metric: 82.00% valid circuits, 49.08 Jaccard, 60.5% functional correctness, versus Code-L2 at 78.16%/45.97/33.0 and Code-L3 at 76.40%/15.46/6.0. The sharpest contrast is between Code-L2 and Code-L3, which differ only in wire specification: netlist Jaccard collapses from 45.97 to 15.46 and connection errors rise from 1.76 to 6.76 per design, establishing pin-name connectivity as the single most consequential element of the representation. Removing CoT synthesis drops valid circuits to 53.40% and functional correctness to 14.0%, indicating distilled reasoning traces carry substantial weight. The raw KiCad file representation yields only 32.45% valid circuits and 3.0% functional correctness.
Comparison with frontier models. On the held-out test set, SchGen exceeds GPT-5.2, GPT-o4mini, and Grok-4 across all metrics when those models are prompted with identical APIs and few-shot examples: SchGen reaches 82.00% valid circuits and 60.5% functional correctness against GPT-5.2-L1's 67.89% and 50.0%. All frontier models fail almost entirely on raw KiCad text (pass ratios of 3.95–10.53%, near-zero netlist accuracy). An interesting observation is that prompted frontier models spontaneously adopt relative coordinates and pin-name wiring even when examples do not, which narrows—but does not close—the gap between Code-L1 and lower-level representations for these models. The implication is that the representation's benefits are partially accessible via prompting, but fine-tuning on it yields strictly better spatial and connectivity behavior.
Generalization. On 988 unseen samples from 20 GitHub KiCad projects, SchGen achieves 65.59% valid circuits and 40.65 Jaccard, statistically matching GPT-5.2 (77.02% valid, 40.64 Jaccard) on netlist accuracy despite its far smaller capacity. Note that GPT-5.2 retains higher validity while SchGen matches connectivity quality; the paper attributes SchGen's lower ceiling to its 20B parameter budget but does not analyze the validity gap in detail.
Limitations and open questions
The paper is explicit about several constraints. The dataset derives from SparkFun designs, so domain coverage is bounded by that corpus; scaling to large, complex PCBs is limited both by data availability and by current LLM capability. Advanced PCB constraints (signal integrity, power budgets, manufacturability) are not modeled, and expert review remains necessary for robustness and safety. Evaluation excludes SPICE-based functional checking, so "functional correctness" rests on human judgment rubrics rather than simulation. Open questions include whether the MDL/LZ complexity metrics predict learnability for other hardware generation tasks, whether reinforcement learning beyond SFT with distilled CoT can push functional correctness past the current 60.5%, and how the approach extends to hierarchical multi-sheet schematics typical of production hardware.
Conclusion
SchGen establishes natural-language PCB schematic generation as a tractable learning task by reformulating it as structured code emission over editing primitives with relative placement and pin-name wiring. The evidence supports the paper's thesis that representation choice dominates model scale for this problem: a LoRA-tuned 20B model surpasses frontier LLMs on validity, netlist accuracy, and expert-verified functionality, and generalizes to unseen GitHub designs at parity with GPT-5.2 on connectivity metrics. The remaining gaps—functional correctness below two-thirds, limited constraint modeling, and dependence on human curation in the data pipeline—define the immediate open problems for this line of work.