Triggerless DAQ Systems

• Triggerless DAQ systems are defined by continuous, free-running data acquisition that foregoes a global hardware trigger in favor of timestamped hit streams and local buffering.
• They shift event selection downstream to firmware and software, enabling precise time synchronization and efficient online data reduction through methods like periodic framing and FPGA-based filtering.
• These architectures, exemplified by systems such as J-PET, SPD, and XENONnT, offer enhanced efficiency and reduced deadtime, while contending with challenges related to data volume, buffer limitations, and high-rate transport.

A triggerless data acquisition system is a DAQ architecture in which detector data are acquired in a continuous, free-running, or self-triggered manner without a global hardware trigger defining events at the detector front end. In this model, time synchronization, buffering, event formation, and physics selection are displaced downstream into firmware and software, typically by means of timestamped hit streams, waveform fragments, or time slices. In contemporary usage, the term covers a spectrum that includes strict free-running streaming systems, software-triggered systems that save all above-threshold pulse snippets, and hybrid designs that combine continuously digitized or self-triggered subsystems with later software selection (Korcyl et al., 2016, Aprile et al., 2022, Sabia, 21 Feb 2025, Afanasyev et al., 16 Sep 2025, Zhang et al., 2024, Aalbers et al., 2024).

1. Conceptual scope and relation to classical T/DAQ

Classical high-energy-physics T/DAQ evolved around front-end buffering, multi-level trigger hierarchies, and selective event building because detector information had to be held pending a trigger decision, while dead time and readout latency had to remain controlled. In that framework, the dead-time contribution of trigger latency and local readout can be expressed as

$$\left( \sum^N_{i=2} R_{i-1} \times L_i \right) + R_N \times T_{\mathrm{LRO}},$$

with $R_i$ the rate after trigger level $i$, $L_i$ the latency of trigger level $i$, and $T_{\mathrm{LRO}}$ the local readout time (Ellis, 2010). Triggerless architectures do not remove these constraints so much as relocate them: the bottleneck shifts from early trigger acceptance to sustained transport, buffering, online reduction, and software event assembly.

In the strongest sense, triggerless DAQ means continuous or free-running readout without preliminary event selection. The J-PET scanner is an explicit example: it performs continuous readout of digitized data without preliminary selection, packages data into UDP fragments every $20~\mu\mathrm{s}$ at a $50~\mathrm{kHz}$ Readout Request rate, and reaches up to $8~\mathrm{Gbps}$ aggregate throughput (Korcyl et al., 2016). The SPD design is similarly explicit that the combination of background processes, event rate, and event-selection conditions makes a classical trigger system impractical, so all front-end signals above threshold are timestamped and read out in a triggerless, free-running architecture (Afanasyev et al., 16 Sep 2025).

A common misconception is that triggerless must mean permanent storage of every ADC sample. Several major systems do not operate that way. XENONnT is triggerless “for the most part,” but it stores every signal that exceeds the digitization thresholds rather than continuously archiving all raw waveforms (Aprile et al., 2022). PandaX-4T uses channel-by-channel Dynamic Acquisition Window logic that continuously monitors samples and stores waveform snippets around self-triggers (Yang et al., 2021). XENON1T continuously digitizes and buffers per-channel pulses, but global event definition is deferred to a later software stage (Aprile et al., 2019). A useful interpretation is that triggerless DAQ is primarily defined by the absence of an early detector-wide hardware event decision, not by mandatory archival storage of all raw samples.

2. Time bases, synchronization, and temporal granularity

Because event identity is no longer provided by a global trigger accept, triggerless DAQ is fundamentally a timing problem. The most common organizing primitives are timestamps, periodic readout frames, time slices, and synchronized slice markers.

J-PET illustrates periodic framing. Slave modules continuously register signal hits and, at each $50~\mathrm{kHz}$ Readout Request, package the data accumulated over one $R_i$0 interval into a UDP packet marked with the Readout Request sequence number and module ID; Event Building later reconstructs detector-wide states by grouping fragments from the same readout period (Korcyl et al., 2016). SPD adopts a more explicitly hierarchical time model: data are organized into slices of $R_i$1–$R_i$2 and frames of $R_i$3–$R_i$4, with timestamps measured relative to the start of the frame (Afanasyev et al., 16 Sep 2025). DarkSide-20k uses Time Slice Markers distributed to all digitizers so that Front End Processors can package data into detector-wide Time Slices, which are then dispatched to Time Slice Processors; neighboring slices overlap by the maximum electron drift time, introducing about $R_i$5 duplicated events (Sabia, 21 Feb 2025). XENONnT instead partitions the stream into $R_i$6–$R_i$7 chunks with $R_i$8 overlap on both sides, then trims at quiet intervals so signals are not split across chunks (Aprile et al., 2022).

Precise clock distribution is correspondingly central. SPD uses White Rabbit to distribute a $R_i$9 global clock with $i$0 period, targeting relative phase deviation no larger than $i$1 and phase jitter no larger than $i$2 rms (Afanasyev et al., 16 Sep 2025). DarkSide-20k distributes a phase-aligned clock from a disciplined rubidium standard through a Global Data Manager and Crate Data Managers, and validation with common sine-wave injection showed channel-to-channel and board-to-board time shifts below $i$3 (Acerbi et al., 3 Apr 2026). PandaX-4T uses common external clock signals generated by a shared oscillator and distributed through custom fanout modules, with synchronous common acquisition start; in offline analysis, S1 and S2 are combined within a $i$4 window, chosen to cover the full TPC drift time (Yang et al., 2021). XENONnT distributes a common $i$5 clock and injects a $i$6 GPS synchronization pulse, ultimately reaching subsystem synchronization precision of about $i$7 after correction of fixed offsets (Aprile et al., 2022).

3. Front-end acquisition, buffering, and local reduction

Triggerless systems typically replace a detector-wide trigger by much more local logic: per-channel thresholding, self-triggered snippet capture, zero suppression, feature extraction, or short-word concentration. The front end therefore becomes the first reduction layer rather than the place where event selection ends.

PandaX-4T is a canonical example of local waveform capture. Each PMT channel independently identifies pulses above threshold with the CAEN V1725 Dynamic Acquisition Window firmware, stores a configurable number of pre-trigger and post-trigger samples, and tags each waveform fragment with trigger time tag and channel number. For commissioning, the threshold for 3-inch PMTs was 20 ADC counts, about $i$8 PE, and the system used 10 MB/channel on-board buffers with readout up to 85 MB/s per digitizer (Yang et al., 2021). J-PET shows a different front-end philosophy: analog PMT pulses are split into four thresholds, discriminated using LVDS input buffers inside FPGA fabric, timed on both rising and falling edges with $i$9 resolution, and buffered up to 54 complete signals per channel between readouts (Korcyl et al., 2016).

Near-triggerless dark-matter DAQs have converged on continuous digitization plus real-time FPGA waveform analysis. LZ continuously samples 1276 channels at 100 MHz and 14 bits, stores them in circular waveform buffers, and applies digital filters matched to S1 and S2 pulse widths so that reduced quantities such as hit vectors, multiplicity counts, pulse area, and total sums can drive selective extraction of waveform regions (Druszkiewicz, 2015). The later FADR implementation keeps this architecture but details the on-board FIR filters and waveform sparsification: Pulse Only Digitization stores 32 pre-samples and 32 post-samples around threshold crossings, while trigger decisions use S1 and S2 filters on raw continuous waveforms rather than on the sparsified payload (Aalbers et al., 2024).

DarkSide-20k pushes this model to larger scale with 48 CAEN VX2745 digitizers, 64 channels per board, 16-bit ADCs, and 125 MS/s sampling. A 64-coefficient FIR filter, local time-over-threshold logic, configurable pre-trigger and post-trigger regions, maximum segment length, decimation, and lossless compression are all implemented in firmware; the reported compression factor is better than 2 (Acerbi et al., 3 Apr 2026). This demonstrates a recurring triggerless design pattern: continuous ADC sampling is economically feasible only if waveform export is already segmented and compressed before it reaches the software farm.

At the transport boundary, triggerless systems often need word-level concentration rather than only waveform selection. The BNRO-based concentrator addresses exactly this problem: it removes non-DAQ words, densely packs useful short words into wider output records while preserving order, scales to 16 inputs in hardware and 32 in simulation, uses no BRAM in the concentrator itself, and achieved 128 Gb/s for a 16-input, 32-bit, 250 MHz configuration (Zabołotny, 2023). This is a front-end data-movement primitive rather than an event builder, but it solves a central triggerless bottleneck: converting many sparse narrow links into an efficient host-facing stream.

4. Event building, software triggering, and online analysis

If the front end no longer defines events, event building must be reconstructed from time-correlated fragments. This can be done with databases, detector-specific software triggers, time-slice farms, or asynchronous framework layers.

XENON1T is a well-defined software-triggered case. Per-channel threshold-crossing pulse snippets are converted into MongoDB documents containing timestamp, module number, channel number, waveform payload, and identifiers. The software trigger scans only indexed metadata, not waveform payload, looking for S1-like coincidences within about 100 ns and S2-like structures over longer intervals; trigger thresholds are 50 pulses for S1 and 60 pulses for S2, and accepted activity defines a 1 ms event window (Aprile et al., 2019). XENONnT removes the XENON1T software trigger for data retention and instead stores all thresholded data, but higher-level event building remains software-defined: strax selects a triggering S2-like peak larger than 100 PE and constructs an event window from 2.45 ms before to 0.25 ms after that peak (Aprile et al., 2022).

TAO shows how software triggering is integrated in a mixed-mode DAQ. Detector fragments are assembled by timestamp or trigger number, WT uses a multiplicity or nHit software trigger, TVT uses a layer-coincidence trigger, accepted data are compressed, and the final storage stage sorts detector data by timestamp, merges fragments from all subsystems, and writes them to disk (Zhang et al., 2024). DarkSide-20k generalizes this to a time-slice farm: Front End Processors perform baseline subtraction, matched filtering, hit finding, and reduction to hit-level quantities, then a Pool Manager dispatches time slices to Time Slice Processors for whole-detector reconstruction, classification, and further reduction, with an estimated reduction from about 3 GB/s at the digitizer level to about 60 MB/s on permanent storage in standard running (Sabia, 21 Feb 2025).

The same architecture can support online machine-learning analysis. A dedicated triggerless pipeline for anomaly detection uses an FPGA first stage to reconstruct local muon stubs, DMA transfer to host memory, cuDF-based GPU preprocessing to identify events and derive features, and GPU-accelerated statistical anomaly detection with the NPLM framework; preprocessing throughput exceeds $L_i$0 for large batches (Grosso et al., 2023). This shows that triggerless DAQ is not equivalent to “no online processing”; in many modern systems it means that online processing occurs later and with richer context.

5. Architectural variants and representative systems

The literature does not use a single rigid definition of triggerless DAQ. A useful classification is therefore comparative rather than doctrinal.

Variant	Representative systems	Characteristic property
Strict or free-running triggerless	J-PET, SPD, DarkSide-20k	Continuous or free-running acquisition without a detector-wide hardware trigger
Software-triggered or quasi-triggerless	XENON1T, XENONnT, PandaX-4T	All above-threshold pulse snippets are saved; global event definition is later software or offline logic
Trigger-minimized or hybrid	LZ/FADR, TAO, AHCAL, EUDAQ2-based integrations	Continuous digitization or self-triggered front ends coexist with selective extraction, mixed hardware/software triggers, or integration-layer timestamp modes

J-PET and SPD are the clearest free-running cases: J-PET continuously records digitized data without preliminary selection, while SPD states that a classical trigger is “hardly realizable” and adopts a triggerless free-running design with timestamped hits, slices, and frames (Korcyl et al., 2016, Afanasyev et al., 16 Sep 2025). DarkSide-20k explicitly describes continuous, triggerless digitization with later reduction in FEP and TSP farms (Acerbi et al., 3 Apr 2026).

XENON1T and XENONnT are quasi-triggerless in a narrower, detector-specific sense. XENON1T defers the global trigger to software while storing per-channel pulse snippets (Aprile et al., 2019). XENONnT stores every signal exceeding per-channel digitization thresholds and postpones event definition to strax, but it does not record every continuous ADC sample (Aprile et al., 2022). PandaX-4T is triggerless at the global-event level but implements local per-channel threshold-triggered waveform capture (Yang et al., 2021).

Hybrid and trigger-minimized systems are equally important. LZ and FADR continuously digitize all channels and base retention on on-board FPGA feature extraction rather than on an external trigger path (Druszkiewicz, 2015, Aalbers et al., 2024). TAO is explicitly mixed-mode: the central detector path is hardware-triggered upstream of the DAQ, while WT and TVT are software-triggered in the DAQ (Zhang et al., 2024). The CALICE AHCAL is self-triggered at the SPIROC front end but windowed by acquisition, conversion, and readout phases, and beam-test mode adds external trigger validation (Kvasnicka, 2017). EUDAQ2 does not claim native full triggerless streaming, but it supports direct-save, timestamp-based synchronization, trigger-number-based synchronization, arrival-order modes, and custom synchronization methods, making it suitable as an integration layer for triggerless-like or mixed-trigger systems (Liu et al., 2019).

6. Benefits, performance envelopes, and limitations

The principal benefit of triggerless DAQ is the postponement of selection until more information is available. In rare-event detectors this directly lowers threshold risk. PandaX-4T states that dark-matter searches are no longer affected by efficiency loss from external triggers; the average self-trigger efficiency for 3-inch PMTs is 96%, the system achieved more than 450 MB/s, and the lower S2 analysis threshold was reduced to 80 PE compared with 100 PE in the final PandaX-II WIMP analysis (Yang et al., 2021). XENON1T reports over 97%—more specifically, over 98% in the detector center—efficiency at recognizing interactions at the analysis threshold, readout bandwidth over 300 MB/s, and less than 1% deadtime in dark-matter-search mode (Aprile et al., 2019). XENONnT extends this to an integrated three-subsystem DAQ with livetime above 99% in normal operation, about 90% during most high-rate calibrations, and sustained calibration readout rates exceeding $L_i$1 MB/s, while collecting more than 2 PB during commissioning and the first science run (Aprile et al., 2022).

At larger scale, triggerless architectures rely on staged online reduction. DarkSide-20k expects about 3 GB/s at digitizer level and about 60 MB/s to permanent storage in standard operation; its one-quarter “Quadrant” demonstrator sustained 250 MB/s per digitizer for 300 hours under stress test (Acerbi et al., 3 Apr 2026). SPD is designed to scale from roughly 180,000 channels to more than 600,000 channels with throughput around 20 GB/s or more, illustrating that triggerless DAQ is also a response to high-rate nuclear-physics environments where classical triggers are judged impractical (Afanasyev et al., 16 Sep 2025).

The limitations are equally structural. Data volume, buffer occupancy, and transport pressure do not disappear when a hardware trigger is removed. PandaX-4T observed negligible busy in standard dark-matter conditions but noticeable systematic effects in a $L_i$2Cs run at 120 MB/s total and 11 MB/s from one digitizer (Yang et al., 2021). XENONnT reports that data quality deteriorates above about 250 MB/s because of pileup, and high-rate calibrations accept about 10% deadtime from busy and high-energy veto logic (Aprile et al., 2022). AHCAL and TAO show another limitation: many systems described as triggerless are in fact windowed, phase-separated, or mixed-mode, because finite front-end memory, detector heterogeneity, or operational simplicity still favor hybrid solutions (Kvasnicka, 2017, Zhang et al., 2024).

Taken together, the literature shows that triggerless DAQ is not a single implementation but an architectural family. Its defining move is the displacement of event definition away from a fast hardware trigger and toward precise timing, distributed buffering, and software reconstruction. The resulting systems range from free-running hit streaming to software-triggered pulse buffering and mixed-mode frameworks, but all share the same central principle: event selection is deferred until a larger fraction of detector information is available.