Single-Transistor Encrypted Cell

Updated 10 December 2025

Single-Transistor Encrypted Cell is an advanced in-memory device that uses ferroelectric FETs to encode XOR logic and secure data directly within memory arrays.
It leverages back-gated Schottky barrier design and polarization-induced threshold shifts to eliminate complementary circuitry, reducing area and energy consumption.
Performance benchmarks indicate a cell area of ~0.04 µm², energy of ~0.3 pJ/bit, and 10 ns propagation delay, making it ideal for secure storage and compute-in-memory applications.

The in-memory single-FeFET XOR scheme leverages the nonvolatile electrical tunability and direction-dependent current conduction of ferroelectric field-effect transistors (FeFETs) to realize digital XOR logic and data encryption entirely in hardware, within memory arrays. By encoding a logic or ciphertext bit directly into the FeFET threshold voltage, this approach eliminates complementary circuitry and maximizes integration density while reducing energy and latency for compute-in-memory and secure storage workloads.

1. Device Physics and Structure

FeFETs relevant to this scheme employ a back-gated Schottky barrier configuration, typically fabricated on MoTe₂ channels (~10 nm) with Al₂O₃ dielectrics (~10 nm) and a thick ferroelectric CuInP₂S₆ (CIPS) layer (~162 nm). Two top programming gates overlap the source/drain contacts and, when pulsed at ±5 V for several microseconds, locally set the ferroelectric polarization. The polarization state—P⁺ (electron-doping) or P⁻ (hole-doping)—modifies the interfacial charge $Q_p$ , thus shifting the effective Schottky barrier and the transistor threshold voltage $V_{th}$ .

The key device equations are as follows:

Channel current: $I_{ds} \approx \mu \cdot C_{ox} \cdot (W/L) \cdot [V_{GS} - (V_{th0} \pm Q_p/C_{ox})] \cdot V_{DS} - ½ V_{DS}^2$
Threshold shift by polarization: $\Delta V_{th} = \pm Q_p/C_{ox}$ The polarization charge $Q_p$ and associated hysteresis window (∼3 V) underlie the nonvolatile logic-state encoding (Zhao et al., 2023).

2. XOR/XNOR Logic Realization in a Single FeFET

The XOR operation is implemented by exploiting FeFET’s dual threshold states. Logic inputs are mapped as follows:

Search input ( $A$ ): Applied to the gate
Stored bit ( $B$ ): Encoded in FeFET polarity—P⁺ (n-type, $V_{th}$ negative shift) or P⁻ (p-type, $V_{th}$ positive shift)
Readout: A match line is pre-charged and bias is applied ( $V_{DS}=+2$ V)

For XNOR-style matching, only a gate voltage/polarity pair with $A=B$ will yield a current above threshold and a “match” flag, while all other combinations remain subthreshold. For XOR, the sense amplifier or logic mapping is inverted so a current pulse marks $A \ne B$ .

Search ( $A$ )	Stored ( $B$ )	FeFET Type	$V_{GS}-V_{th}$	$I_{ds}$	Match/XOR Output
0	0	p-type	Large positive	$\approx 0$	0
0	1	n-type	Negative	$\approx 0$	0
1	0	p-type	Large positive	$\approx 0$	0
1	1	n-type	Lower, positive	$\gg 0$	1

This structure eliminates the need for complementary circuits—enabling single-device XOR/XNOR computation and large area savings (Zhao et al., 2023, Ovy et al., 3 Dec 2025).

3. In-Memory CAM and Encryption Array Architectures

In the context of content-addressable memory (CAM), each FeFET stores one bit (by programming its ferroelectric state), with the gate serving as the search line and the drain connected to a match line. XNOR matching flags rows that fully match; multi-bit parallelism is achieved by organizing FeFETs in NAND or NOR configurations.

For encrypted memory, the “ciphertext” bit is mapped directly to FeFET threshold: $C = P \oplus K$ , with $C=0$ (LVT) or $C=1$ (HVT). During decryption, key bits $K_i$ control columnwise drain/source biases, and a single read pulse produces the XOR result $P = C \oplus K$ in one cycle.

Scheme	Devices per bit	Area Overhead	Write Cycles (Enc)	Read Cycles (Dec)
AES (external)	+0.00309mm²	Block-level	115.5	121
Prior 2-FeFET XOR	2	100%	5	16
1T-FeFET XOR	1	0%	2.5	8

In NOR-arrays, the summed discharge current provides an analog output for Hamming distance computations (Zhao et al., 2023). Encryption arrays further support multi-level cell (MLC) extensions with four threshold levels for two-bit encoding (Ovy et al., 3 Dec 2025).

4. Performance Characteristics and Benchmarking

The single-FeFET structure yields:

Cell area: ~0.04 µm² (versus ~1.0 µm² for 10T SRAM-CAM)
Energy per operation: $\sim0.3$ pJ/bit
Propagation delay: $\sim10$ ns for 32-bit reads
Throughput: Encryption/decryption up to 1280/400 Mbps (25 MHz, 128x128 array)
Latency reduction: 50% (vs. prior FeFET XOR) and up to 95% (vs. AES) for CNN inference on TPU-accelerators (examples: AlexNet, MobileNet, ResNet-18)

Power consumption is negligible, with dynamic energy dominated by fJ-level writes and nW-level reads, contrasting with the higher block-level power of AES engines (Ovy et al., 3 Dec 2025). In multi-bit MLC arrays, additional read cycles are required but yield two bits per transistor.

5. Scaling, Variability, and System Integration

Device variability in $Q_p$ and $V_{th}$ can induce sensing errors across large arrays. Proposed countermeasures include:

Per-row sense amplifier calibration
Hierarchical match-line segmentation
Error-correcting codes and majority voting for extreme-scale deployments
Programming disturb mitigation via local write buffers or write-verify schemes

Sneak paths in NOR-style arrays necessitate segmented match lines and gating transistors. Adaptive sense amplifiers are recommended to accommodate cycle-to-cycle and device-to-device $V_{th}$ variation (Zhao et al., 2023). For multi-bit analog in-memory compute, intermediate ferroelectric ratios and programmable $Q_p$ enable multi-level encoding and distance measurement.

A plausible implication is that with robust peripheral circuits and calibration, 1T-FeFET XOR schemes can scale to multi-megabit compute engines for search, classification, encryption, and low-latency neural network inference.

6. Applications and Broader Impact

Single-FeFET XOR schemes have direct utility in:

Ultra-dense encrypted memory arrays (no density loss relative to plaintext storage)
Compute-in-memory accelerators for data-intensive tasks, especially pattern matching and Hamming distance calculations
High-throughput, energy-efficient machine learning hardware, evidenced by benchmarked CNN inference inside systolic arrays

Their direction-dependent conduction and direct threshold-based encoding uniquely position FeFET arrays for simultaneous logic, memory, and security functions, with broad applicability from edge devices to high-performance r-ASICs and AI accelerators.

7. Future Directions and Open Challenges

Key research directions include:

Extension of FeFET schemes to multi-level cells for analog and multi-bit processing
Integration with hierarchical and adaptive sense architectures for extreme scale-out
Addressing device-level variability through enhanced calibration or error correction
Exploring new programming waveforms and device stack materials for optimized endurance, retention, and switching speed

This suggests ongoing innovation in circuit partitioning, calibration protocols, and materials science is required for deployment in advanced in-memory computing and secure storage architectures. Both fundamental device physics and system-level engineering remain active domains for the further evolution of single-FeFET XOR logic and encryption (Zhao et al., 2023, Ovy et al., 3 Dec 2025).