Synchronous Ethernet (SyncE) Technology

• SyncE is a networking technology that embeds a reference clock within Ethernet data streams, ensuring physical-layer frequency synchronization with low jitter.
• It uses PHY clock recovery and PLL conditioning to distribute a common 125 MHz signal over 1000BASE-T/KX links, enhancing timing precision.
• Widely applied in telecom, distributed data acquisition, and scientific instrumentation, SyncE reduces system complexity by eliminating separate clock distribution.

Synchronous Ethernet (SyncE) is a networking technology designed to provide physical-layer frequency synchronization over standard Ethernet transports, enabling all devices in the network to share a high-quality, low-jitter clock reference. Unlike the asynchronous nature of conventional Ethernet, where the PHYs (physical layer devices) operate off free-running local oscillators and only align symbol boundaries through data streams, SyncE embeds a reference clock within the Ethernet PHY data stream, allowing precise clock recovery at the receiver. SyncE is widely adopted in distributed data acquisition, scientific instrumentation, and telecom applications that require deterministic timing, low jitter, and scalable clock distribution over standard Ethernet infrastructures.

1. Principles and Architecture of SyncE in Modern Systems

SyncE extends conventional Ethernet standards by enabling the distribution of a common clock frequency to all nodes over standard copper or backplane links, supporting both 1000BASE-T and 1000BASE-KX interconnects. A typical architecture comprises an arrangement in which a master PHY embeds its transmit clock (e.g., 125 MHz for Gigabit Ethernet) into the data stream, which is then elastically recovered by the slave PHY at the remote end. This recovered SyncE clock is further conditioned and distributed internally within FPGAs or system-on-chip devices via PLLs. State-of-the-art FPGA-based stacks, such as the design by Födisch et al., implement the MAC and all networking protocol layers (Ethernet, ARP, IP, ICMP, UDP, PTP) as pipelined IP cores interfaced directly with high-throughput application logic and slow-control microcontrollers (Födisch et al., 2015).

In laboratory and DAQ environments, SyncE eliminates the need for separate clock-and-trigger fan-out trees. For example, in the Pixie-Net system for radioactive gas detection, the SyncE-capable Texas Instruments DP83640 PHY delivers a recovered reference clock to all digital logic and ADCs, replacing the conventional method of manually distributing synchronous clocks across modules (Hennig et al., 2019).

2. Clock Recovery, Distribution, and Physical-Layer Implementation

SyncE exploits the fact that an Ethernet PHY’s physical signaling layer can convey not just encoded data, but also the master-side transmit clock. In 1000BASE-T, the master’s 125 MHz clock is embedded via symbol encoding (8b/10b in BASE-T PCS), allowing the slave PHY to recover the clock from the equivalent data stream. In 1000BASE-KX (commonly used with MicroTCA backplanes), the Xilinx GTX transceiver’s PCS/PMA core accomplishes analogous clock recovery. At the system level, the architecture is typically:

PHY(master) → [Ethernet cable/backplane] → PHY(slave) → FPGA PLL → MAC & timestamp logic

Depending on design choices, the recovered clock may be routed directly via FPGA buffer trees or conditioned by a PLL (typical factor: multiplier/divider = 8). Using an on-chip PLL provides flexible clock tree distribution but introduces additional jitter (~6–20 ps, measured), while direct routing through the buffer tree offers marginally lower jitter at the cost of scalability or fanout (Födisch et al., 2015). In the Pixie-Net system, the DP83640’s recovered REF_CLK is routed to the FPGA fabric, serving the ADCs and digital pulse processing logic, effectively locking all sampling elements to the network-distributed SyncE clock (Hennig et al., 2019).

3. Precision Time Protocol (PTP) and Joint Synchronization

While SyncE enforces common frequency and very low jitter across all endpoints, it does not resolve the absolute phase or time origin: all devices may be ticking at the same rate but with arbitrary phase offsets due to transmission path delays. The IEEE-1588 Precision Time Protocol (PTP) is layered over Ethernet/IP networks to achieve absolute time alignment. PTP exchanges timestamp packets (“Sync”, “Delay_Req”, “Delay_Resp”) and corrects for propagation delay and offset up to the resolution of the local clock.

State-of-the-art implementations couple SyncE-distributed clocking and PTP timestamp logic. Timestamp units operate off the SyncE-derived clock (e.g., 125 MHz, giving 8 ns resolution per tick); generated pulses-per-second (PPS) are then phase aligned via PTP corrections. The combined effect is sub-tick absolute time alignment—for example, in Födisch et al., σ_PPS alignment was measured as 58.9 ps over 13 hours, with detector-limited bias ~3.94 ns (fixed phase error non-removable by pure PTP without hardware calibration) (Födisch et al., 2015). In the Pixie-Net setup, the DP83640 provides hardware timestamping for PTP and a reference 250 MHz clock for ADCs, with a hybrid approach allowing initial phase-gating via a PTP-driven GPIO (Hennig et al., 2019).

Mathematically, the offset correction in a two-step PTP exchange is given by:

$\theta = \frac{(t_2 - t_1) + (t_3 - t_4)}{2}$

where $t_1$ and $t_2$ are the master–slave sync send/receive times, and $t_3$, $t_4$ are the slave–master delay request/response times (Födisch et al., 2015, Hennig et al., 2019).

4. Measured Performance and Quantitative Evaluation

Benchmarking SyncE implementations requires assessment of both synchronous clock jitter and network data throughput. Representative metrics from recent FPGA-based and detector-oriented designs include:

Metric	Sys/PHY	Measured Value	Reference
Clock–clock jitter (1000BASE-T/KX, PLL)	TI DP83865, Marvell	55.1–70.3 ps	(Födisch et al., 2015)
SyncE-only time-diff (FWHM, pulser)	DP83640, Pixie-Net	0.19 ns (200 ps)	(Hennig et al., 2019)
SyncE-only time-diff (FWHM, detector)	DP83640, Pixie-Net	0.79 ns	(Hennig et al., 2019)
UDP throughput (MTU=1500/Jumbo=9000 B)	TI DP83865/GTX	114–118 MiB/s	(Födisch et al., 2015)
σ_offset(PPS) (SyncE + PTP, 13h)	FPGA+PHY	58.9 ps	(Födisch et al., 2015)

Clock phase noise and frequency stability are quantified by Allan deviation, with the DP83640 plus a high-quality SyncE switch achieving deviations in the $10^{-11}$ range for $\tau$ up to 1 s (Hennig et al., 2019). In LaBr$_3$ detector timing experiments, SyncE plus PTP yielded FWHM of 0.8 ns, limited by the detector rather than the electronics (Hennig et al., 2019). UDP payload throughput reached 99.3% of the theoretical line rate for jumbo MTU operation, with only minimal deviation in measurement versus calculation (Födisch et al., 2015).

5. Key Mathematical Models and Formulae

A SyncE-enabled data path exposes several quantitative models:

• Theoretical UDP Throughput:

$T(P) = \frac{8P}{8P + 9 + 46 + 12} \times L$

where $P$ is UDP payload (bytes), header and preamble sizes as specified, and $L$ is line rate (1 Gbit/s) (Födisch et al., 2015).

• Jitter Summation (Uncorrelated Sources):

$$\sigma_{\text{total}} = \sqrt{\sigma_{\text{PHY}}^2 + \sigma_{\text{PLL}}^2 + \sigma_{\text{board}}^2}$$

enabling the calculation of overall RMS jitter from each component (Födisch et al., 2015).

• Allan Deviation for Frequency Stability:

$$\sigma_y(\tau) = \sqrt{ \frac{1}{2}\left\langle [\overline{y}(t + \tau) – \overline{y}(t)]^2 \right\rangle }$$

where $\overline{y}(t)$ is the average fractional frequency over $\tau$ (Hennig et al., 2019).

These formulae support both performance benchmarking and physical-layer engineering of SyncE networks.

6. Design Trade-offs, Limitations, and Future Directions

Selecting between on-chip PLL-based clock trees and direct buffer-based distribution involves trading jitter/latency for clock tree flexibility and fan-out. Bypassing the PLL lowers total jitter but reduces the capacity to distribute synchronous clocks flexibly across a large FPGA. Data-path organization (data-pull vs. data-push) impacts internal buffer usage, with pull-based designs enabling minimal buffering at a small cost in complexity (Födisch et al., 2015).

Limitations are pronounced in specific aspects:

• SyncE provides only frequency alignment; absolute phase offset due to fixed link delays persists and must be calibrated per system setup or through a one-time PTP “start” strobe (Hennig et al., 2019).
• Timestamp precision is capped by the clock frequency of the timestamp unit (e.g., 8 ns at 125 MHz) unless sub-nanosecond phase measurement circuitry (e.g., White Rabbit) is introduced (Födisch et al., 2015).
• Low-jitter in practice (sub-100 ps) is highly dependent on proper switch selection and pre-measurement of fixed delay offsets. Non-PTP/non-SyncE switches induce significant wander and degradation (Hennig et al., 2019).
• For extreme time-of-flight applications (<200 ps), SyncE is outperformed by dedicated ps-class timing networks.

Potential improvements include integrating external ultra-low jitter PLLs, implementing hardware-based phase measurement and delay tuning elements, migrating to advanced timestamping within PHY/MAC, and adopting techniques from projects such as White Rabbit for hardware-level phase calibration (Födisch et al., 2015).

7. Practical Applications, Impact, and Scalability

SyncE enables modular, scalable timing architectures for DAQ and large sensor arrays where conventional clock/trigger distribution is infeasible or cost-prohibitive. In the Pixie-Net system for distributed radioactive gas detection, up to 100 modules can be synchronized via standard Cat-6/Cat-7 cabling through a single SyncE-aware switch, with timing FWHM down to sub-ns across detectors. The elimination of separate clock and trigger cables drastically reduces system complexity and installation effort (Hennig et al., 2019).

In distributed DAQ solutions adopted in medical imaging and experimental physics, FPGA-based SyncE stacks facilitate high-throughput UDP data transfer, while sustaining deterministic latency and phase-coherent operation over both twisted-pair (1000BASE-T) and backplane (1000BASE-KX) links. This supports applications with fine-grained coincidence windows and tight time-stamping requirements (Födisch et al., 2015).

The direct coupling of PHY-level clock recovery, minimal internal buffering, and PLL-conditioned clock trees has established SyncE as a key enabler of time-synchronized, deterministic data transport in networked instrumentation and measurement systems.