Superconducting Diodes: Unidirectional Zero-Resistance

• Superconducting diodes are nonreciprocal devices that enable zero-resistance current transport in one direction by breaking time-reversal and inversion symmetries.
• They leverage innovative architectures like twisted cuprate junctions, strain-engineered films, and nanowire geometries to achieve tunable rectification and memory functionalities.
• Key performance metrics include diode efficiencies up to 100% and quantized digital outputs, supporting applications in superconducting logic and quantum circuits.

A superconducting diode is a nonreciprocal superconducting device that supports dissipationless supercurrent flow preferentially in one direction, with the transition to resistive behavior in the opposite direction. Unlike conventional rectifiers that operate via dissipative quasiparticle transport, superconducting diodes (SDs) enable unidirectional, zero-resistance transport, often with digitally quantized, noise-immune outputs and in some architectures, field-free tunability and memory functionality. The underlying mechanisms exploit symmetry breaking—both spatial inversion and time-reversal—and manifest across a broad spectrum of materials platforms, device geometries, and operational protocols. SDs now serve as a foundational unit for dissipationless logic, nonvolatile superconducting memories, cryogenic rectifiers, and scalable superconducting quantum circuits.

1. Fundamental Principles and Definition

A superconducting diode effect (SDE) manifests as nonreciprocal dissipationless current: the device maintains zero voltage for supercurrent $I$ in the range $|I_{c}^{-}| < I < I_{c}^{+}$, with critical currents $I_{c}^{+}$ (forward) and $I_{c}^{-}$ (reverse), but transitions to a finite voltage state for $|I|$ exceeding the smaller of these. The diode efficiency is quantified as

$$\eta = \frac{|I_{c}^{+}| - |I_{c}^{-}|}{|I_{c}^{+}| + |I_{c}^{-}|},$$

with $\eta = 1$ denoting a perfect diode. Achieving nonreciprocal transport requires simultaneous breaking of time-reversal symmetry (TRS) and inversion symmetry (IS). TRS can be broken by static magnetic fields, trapped magnetic flux, microwave-induced effective fields, or engineered magnetization gradients; IS is typically broken via device geometry, engineered structural inversion, moiré or twist engineering, strain, or by applied AC drives with controllable phase.

Superconducting diodes fall into two broad operational classes:

• Classical SDs: Unidirectional supercurrent is achieved by controlling the critical current, with the reverse direction entering a dissipative state populated by quasiparticles.
• Quantum SDs (QSDs): Entire operation is restricted to phase-coherent Cooper-pair transport regimes, with the device never entering a resistive quasiparticle branch, instead using externally driven Shapiro plateaus or other quantized states for output (Wang et al., 29 Sep 2025).

2. Device Architectures and Symmetry Breaking Mechanisms

2.1 Twisted-Cuprate Quantum Superconducting Diode

Twisted high-$T_c$ cuprate Josephson junctions (Bi$_2$Sr$_2$CaCu$_2$O$_{8+x}$, Pb-Bi2212) with a controlled twist angle $\theta$ around the $c$-axis are fabricated via cryogenic cold-stacking to better than $0.1^\circ$ precision. Time-reversal symmetry is broken via zero-field current "training", which traps Josephson fluxons in the interface. Post training, a strong nonreciprocity in $I_c^{+}$ and $I_c^{-}$ arises, tunable by microwave irradiation, and enhanced on Shapiro plateaus (Wang et al., 29 Sep 2025).

2.2 Strain-Engineered Zero-Field Diodes

Field-free SDs have been achieved in NbSe$_2$ by applying local uniaxial strain via nanoridge substrates, breaking real-space inversion symmetry and inducing a fixed polar axis. Two orthogonal mechanisms are observed: a strain-induced, field-even SDE in the armchair direction, and a field-induced, band-asymmetric (B-odd) SDE in the zigzag direction. Devices show efficiencies up to $\eta=6.8\%$ at zero field with critical-current differences $\Delta I_c\approx 286$ $\mu$A (Li et al., 28 Sep 2025).

2.3 Planar and Nanowire Geometries

Single nanowire SDs exploit mesoscopic geometric asymmetry: a constricted NbTiN nanowire segment with an expanded triangular pad acts as the core, with perpendicular magnetic field breaking TRS. The combination of local current crowding and asymmetrically suppressed vortex barriers gives polarity-dependent depairing, yielding $\eta>24\%$ at 2 K (Zhang et al., 2023).

2.4 Conventional Thin Films and Hybrid S/F Devices

Superconducting thin films (Nb, V) with engineered edge asymmetries and/or proximity-induced ferromagnetic order (EuS overlays) exhibit strong rectification—up to $\eta\approx 65\%$—due to Meissner screening currents and asymmetric vortex-surface barriers. In V/EuS, zero-field, nonvolatile SD operation is achieved with polarity set by the remanent magnetization direction (Hou et al., 2022, Ingla-Aynés et al., 2024).

2.5 Circuit-level and Drive-Induced SDE

Zero-field SDE is also realized at the circuit level: a finite lead resistance $R_L$ in combination with a Cooper-pair transistor (CPT) induces asymmetric chemical potential shifts under positive and negative bias. This non-intrinsic SDE is fully configurable, switchable, and scalable, with efficiency up to $\eta\sim 60\%$ (Shi et al., 23 May 2025). In an alternative approach, a biharmonic AC drive of a conventional Josephson junction yields ideal, field-free rectification ($\eta\rightarrow 1$) by temporal symmetry-breaking alone (Borgongino et al., 11 Apr 2025).

3. Quantitative Performance Metrics

A range of device platforms exhibit high efficiency and broad operational regimes:

Architecture	Max $\eta$	$T_{\mathrm{operation}}$	Zero-Field?	Digital/logic features
Twisted Bi2212 QSD (Wang et al., 29 Sep 2025)	100%	$\geq$77–83 K	Yes (trained)	Quantized steps, AND
Strained NbSe$_2$ (Li et al., 28 Sep 2025)	6.8%	2 K	Yes	N/A
NbTiN nanowire (Zhang et al., 2023)	24%	up to 9 K	No	N/A
V/EuS bilayer (Hou et al., 2022Ingla-Aynés et al., 2024)	65% (single), 51% (bridge)	1.7–6.5 K	Yes (magnetic)	Memory
Circuit-level CPT (Shi et al., 23 May 2025)	60%	8–1000 mK	Yes	Switchable
Biharmonic AC Josephson (Borgongino et al., 11 Apr 2025)	100%	up to 800 mK	Yes	Rapid reconfig.

Nonreciprocity ratios $I_c^{-}/I_c^{+}$ above $10$ have been reported in quantum SDs under field-free, microwave-driven conditions (Wang et al., 29 Sep 2025). Output voltage quantization on the $n$th Shapiro plateau is achieved at $V_n = n(hf/2e)$, with noise fluctuations as low as $0.3\%$ of $hf/2e$ (instrument-limited), conferring substantial resilience against input-current noise (up to $\pm 20\%$) (Wang et al., 29 Sep 2025).

4. Theoretical Formulation and Modeling

Nonreciprocal phenomena in SDs are modeled via several theoretical frameworks:

• Generalized Ginzburg–Landau Functional: Incorporates magnetochiral (odd in momentum) and finite-momentum pairing (FFLO) terms. Nonreciprocity parameter $Q$ and efficiency $\eta\sim h\sqrt{1-T/T_c}/T_c$ have closed-form expressions (He et al., 2021, Ma et al., 17 Feb 2025).
• Resistively and Capacitively Shunted Junction (RCSJ): The CPR is modified to include first, second harmonics, and explicit TRS-breaking terms: $$J(\varphi)=J_{c1}\sin\varphi-J_{c2}\sin2\varphi+J_m\cos\varphi$$ (Wang et al., 29 Sep 2025).
• Microscopic BdG Theory: For Rashba nanowires, self-consistent FFLO calculations reveal that with both linear and higher-order SOC, and transverse/longitudinal fields, diode efficiencies $\eta>45\%$ are achievable due to asymmetric band dispersion and field-induced finite pairing momentum (Bhowmik et al., 2024).
• London-Bean Model: In S/F bilayers, edge-localized stray fields induce Meissner screening currents with spatial asymmetry, directly leading to different vortex-entry barriers for positive and negative current, accounting for the observed diode effect in the absence of SOC (Gutfreund et al., 2023).

5. Logic, Memory, and Quantum Application Scenarios

The robust nonreciprocity and noise immunity of superconducting diodes, especially those with quantized outputs, underpin a variety of advanced functionalities:

• Digitized Logic: QSDs operating on Shapiro plateaus provide multi-valued outputs (e.g., 0, $hf/2e$, $hf/e$), enabling AND gates with three-state logic and rapid microwave-driven state switching (Wang et al., 29 Sep 2025).
• In-Memory and Polarity-Switchable Logic: Devices with Abrikosov vortex-based memory can cycle between reciprocal and two nonreciprocal diode states, with pulse-based write operations (<10$^{-15}$ J/bit, nanosecond scale) and stability over hours (Golod et al., 2022).
• Noise-Resilient Signal Processing: Shapiro-plateau-based diodes offer $>10\times$ lower intrinsic output jitter compared to classical SDs, advantageous for quantum-limited circuit applications (Wang et al., 29 Sep 2025).
• Reconfigurable and Editable Diodes: In LAO/KTO heterostructures, c-AFM lithography enables in situ, nonvolatile editing of diode polarity and efficiency, supporting programmable logic and network reconfiguration (Wang et al., 10 Nov 2025).
• Directional Qubit Coupling: Asymmetric SQUID SDs in cQED architectures provide hardware-level directionality, enabling nonreciprocal entanglement gates (half-iSWAP), dynamic entanglement routing, and microwave signal isolation (Dirnegger et al., 25 Nov 2025).

6. Limitations, Controllability, and Prospects

While quantum SDs (e.g., twisted-cuprate with training and microwave drive) routinely reach perfect efficiency at temperatures $\geq 77$ K, classical SDs targeting higher efficiency face a tradeoff involving device geometry, material selection (edge barriers vs. intrinsic FFLO), and operational bandwidth. Currently, there is no upper fundamental efficiency limit for SDE; several architectures achieve $|\eta|=1$ over broad parameter ranges (field amplitude, AC phase, or circuit topology) (Wang et al., 29 Sep 2025, Borgongino et al., 11 Apr 2025, Sun et al., 13 Jul 2025).

Future avenues include

• Extending operation into the GHz regime (Ingla-Aynés et al., 2024, Dirnegger et al., 25 Nov 2025)
• Integrating SDs into rapid single-flux quantum (RSFQ) and neuromorphic superconducting logic (Wang et al., 29 Sep 2025, Ma et al., 17 Feb 2025)
• Developing 3D multilevel SD circuits by harnessing geometric chirality (e.g., helical geometries, Möbius strips) (Deenen et al., 17 Dec 2025)
• Dynamic, field-free gate-tunable and circuit-level-programmable SDs for scalable digital architectures (Shi et al., 23 May 2025, Mazur et al., 2022)
• Exploring materials and geometric design for topological and higher-order SOC-induced SDE with large, robust efficiency (Bhowmik et al., 2024, Nadeem et al., 2023).

A persistent challenge is to unambiguously distinguish intrinsic SDE (e.g., FFLO-type induced by SOC+Zeeman) from extrinsic mechanisms (e.g., Meissner-edge effects). This requires careful device engineering, e.g., symmetric edge design, and the elimination of residual stray fields (Hou et al., 2022, Ma et al., 17 Feb 2025).

7. References to Key Research and Representative Metrics

The following table summarizes select superconducting diode platforms, referencing principal works and their salient metrics:

System/Platform	Max $\eta$	Special Features	Key Reference
Twisted Bi2212 QSD	100%	$T \geq 83$ K, digital	(Wang et al., 29 Sep 2025)
Strained NbSe$_2$ field-free SDE	6.8%	B-even/odd, patternable	(Li et al., 28 Sep 2025)
Biharmonic-driven JJ diode	100%	Wireless, $>800$ mK	(Borgongino et al., 11 Apr 2025)
NbTiN nanowire diode	24%	Minimal, scalable	(Zhang et al., 2023)
V/EuS thin-film (zero field)	65%	Nonvolatile, memory	(Hou et al., 2022, Ingla-Aynés et al., 2024)
MW-SQUID analytic PSD	100%	Stable with flux tuning	(Sun et al., 13 Jul 2025)
KTaO$_3$-based editable SD	40%	c-AFM tunable	(Wang et al., 10 Nov 2025)
Asymmetric SQUID diode for cQED	$\sim$20%	Qubit coupling, isolation	(Dirnegger et al., 25 Nov 2025)
Gate-tunable Josephson nanowire diode	$\sim$8%	Polarity sign flips	(Mazur et al., 2022)
Circuit-level zero field SD (CPT)	60%	Logic, memory, scalable	(Shi et al., 23 May 2025)
Chiral helix geometric SD	30%	3D, geometry-induced	(Deenen et al., 17 Dec 2025)

All tabulated efficiencies, control modalities, and performance characteristics appear verbatim in the cited arXiv works. A plausible implication is that further improvements in robust quantum SD design will center on combining extrinsic configurability (e.g., via circuit or drive protocol) with high-$T_c$ material systems, to approach and surpass efficiency and functional density milestones necessary for scalable superconducting logic and quantum hardware.