Probabilistic Bits: Fundamentals & Applications

• Probabilistic bits (p-bits) are tunable stochastic units whose binary output follows a sigmoid function controlled by input bias, bridging deterministic logic and probabilistic inference.
• They are implemented across diverse platforms—from FPGA and digital CMOS to nanomagnetic and ferroelectric devices—exploiting inherent device noise for robust sampling and optimization.
• P-bit networks enable scalable, energy-efficient hardware solutions for complex tasks such as Bayesian inference, integer factorization, and quantum simulation.

Probabilistic bits, or p-bits, are classical stochastic units whose instantaneous state fluctuates between two values while the probability of each value is controllable by an input bias. In the hardware-oriented literature, a p-bit is typically formulated as a binary stochastic neuron in either $m_i\in\{-1,+1\}$ or $s_i\in\{0,1\}$ form, and coupled networks of p-bits are used to realize Boltzmann sampling, Ising computation, Bayesian inference, invertible logic, and related probabilistic algorithms. Unlike a deterministic bit, a p-bit continuously exploits fluctuations; unlike a qubit, it does not rely on coherent superposition or entanglement. The term has therefore come to denote a broad class of tunable stochastic primitives spanning digital FPGA emulations, nanomagnetic and magnetic-tunnel-junction devices, ferroelectric transistors, oxide and manganite devices, and polymer memristors (Sutton et al., 2019, Chowdhury et al., 2023).

1. Formal definition and stochastic laws

The canonical p-bit is a binary random variable whose output probability is a sigmoid function of a local input. In the $\{-1,+1\}$ convention, a standard definition is

$$P(m_i=+1)=\frac{1}{1+e^{-2I_i}},\qquad I_i=\beta\sum_j W_{ij}m_j,$$

with $\beta$ an overall gain or inverse pseudo-temperature and $W_{ij}$ programmable couplings. An equivalent update rule is

$$m_i \leftarrow \operatorname{sgn}\!\bigl[\tanh(I_i)+r_i\bigr],$$

where $r_i$ is uniformly distributed on $[-1,+1]$. In the $\{0,1\}$ convention, one often writes

$s_i\in\{0,1\}$0

with $s_i\in\{0,1\}$1 and $s_i\in\{0,1\}$2 (Sutton et al., 2019, Pervaiz et al., 2017, Kaiser et al., 2021).

For reciprocal networks with symmetric couplings, these local stochastic updates are associated with an Ising- or Boltzmann-machine energy. A common form is

$s_i\in\{0,1\}$3

so that the steady-state distribution is Boltzmann-like. In FPGA and circuit implementations this relation is frequently expressed through

$s_i\in\{0,1\}$4

where $s_i\in\{0,1\}$5 controls the effective inverse temperature and the pair $s_i\in\{0,1\}$6 encodes logic, optimization, or inference constraints (Pervaiz et al., 2017, Chowdhury et al., 2023).

The formal role of the p-bit is therefore precise: it is not merely a noisy bitstream generator, but a tunable stochastic neuron whose bias is determined by a weighted field and whose collective dynamics can be designed to sample structured probability distributions. This places the p-bit midway between ordinary deterministic logic and probabilistic graphical-model inference, while retaining a strictly classical operational basis (Kaiser et al., 2021).

2. Update semantics and collective dynamics

A central issue in p-bit systems is the update schedule. In conventional Boltzmann-machine or Ising-annealing hardware, neurons are updated one at a time in a carefully sequenced Gibbs-sampling order. The FPGA “weighted p-bit” architecture embodies this approach explicitly: each p-bit combines local storage of weights and bias, a fixed-point weighted sum, a lookup-table implementation of $s_i\in\{0,1\}$7, and a 32-bit LFSR/comparator, while a 4×4 tile uses a finite-state-machine sequencer that issues 16 one-hot enable signals so that exactly one p-bit updates at a time (Pervaiz et al., 2017).

By contrast, autonomous p-bit architectures remove the global sequencer. In the sequencerless design of Borders et al., each p-bit attempts flips at a steady intrinsic rate set by a small parameter $s_i\in\{0,1\}$8, using only its most recent input. A behavioral model is

$s_i\in\{0,1\}$9

with $\{-1,+1\}$0. Because $\{-1,+1\}$1, actual flips are infrequent and the probability of strongly coupled neighbors flipping simultaneously remains low, allowing high-fidelity Boltzmann sampling without a clocked ordering constraint (Sutton et al., 2019).

At the architectural level, p-computers are commonly described as an $\{-1,+1\}$2-bit RNG array, a problem-specific kernel, and a data collector. The p-bit array generates stochastic samples, the kernel computes new inputs such as $\{-1,+1\}$3, and the data-collector accumulates correlations, histograms, or other observables. This pattern recurs across Bayesian networks, Ising solvers, Monte Carlo engines, and invertible logic (Kaiser et al., 2021).

Large systems need not be fully reciprocal. Directed compositions are common: in ripple-carry adders built from reciprocal full-adder tiles, each tile remains internally reciprocal but carries are wired one-way between tiles, breaking detailed balance globally while preserving useful invertible behavior. More generally, graph-colored pseudo-asynchronous schedules and fully asynchronous Poisson-like update clocks have been proposed to reduce synchronization overhead, and graph sparsification via strongly ferromagnetic “COPY” couplings can reduce local degree while preserving the exact optimum of the encoded problem (Pervaiz et al., 2017, Chowdhury et al., 2023).

3. Physical embodiments

Digital realizations provide a direct, programmable baseline. In the FPGA implementation of “weighted p-bits,” each p-bit fuses its synapse and stochastic neuron into a self-contained module with local registers for one row of the weight matrix, fixed-point arithmetic, a LUT for $\{-1,+1\}$4, and a 32-bit LFSR, with an overhead of roughly 42 LUTs and 33 registers per p-bit on the reported platform (Pervaiz et al., 2017).

Spintronic realizations are the most extensively developed physical p-bits. Low-energy-barrier nanomagnets and superparamagnetic MTJs exploit thermal switching between magnetic states, while bias current or gate-controlled transistor resistance shifts the dwell-time asymmetry and therefore the output probability. In a macrospin model one obtains

$\{-1,+1\}$5

and studies of low-energy-barrier nanomagnets found that reasonable geometric variations do not destroy the programmability of the probability-current characteristic; higher spin polarization further suppresses the spread (Drobitch et al., 2019). This magnetic route also underlies the autonomous nanomagnetic co-processor proposal, where a low-barrier nanomagnet plus CMOS inverter serves as a hardware p-bit (Sutton et al., 2019).

Recent experiments have pushed these ideas toward monolithic integration. A 130 nm CMOS test chip with back-end-integrated sMTJs contained 150 full p-bit cells and showed that fluctuating sMTJ resistance can generate a tunable stochastic digital output with a sigmoid fit characterized by $\{-1,+1\}$6 and $\{-1,+1\}$7 V (Yoon et al., 15 Apr 2026). A separate on-chip 3T-1MTJ demonstration used only 3 transistors plus 1 sMTJ to produce rail-to-rail stochastic output, with average power $\{-1,+1\}$8 at $\{-1,+1\}$9, a dwell time of $$P(m_i=+1)=\frac{1}{1+e^{-2I_i}},\qquad I_i=\beta\sum_j W_{ij}m_j,$$0 ms for one device, and a faster device at $$P(m_i=+1)=\frac{1}{1+e^{-2I_i}},\qquad I_i=\beta\sum_j W_{ij}m_j,$$1s; the same work projected $$P(m_i=+1)=\frac{1}{1+e^{-2I_i}},\qquad I_i=\beta\sum_j W_{ij}m_j,$$2 flip/ns at about $$P(m_i=+1)=\frac{1}{1+e^{-2I_i}},\qquad I_i=\beta\sum_j W_{ij}m_j,$$3 for $$P(m_i=+1)=\frac{1}{1+e^{-2I_i}},\qquad I_i=\beta\sum_j W_{ij}m_j,$$4 ns (Zhang et al., 6 Apr 2026). An earlier integrated core combining stochastic MTJs with monolayer-MoS$$P(m_i=+1)=\frac{1}{1+e^{-2I_i}},\qquad I_i=\beta\sum_j W_{ij}m_j,$$5 FETs established a 3T-1MTJ design space in which MTJ TMR, FET resistance range, and inverter gain jointly determine the smoothness and usable range of the p-bit sigmoid (Daniel et al., 2023).

Ferroelectric and oxide implementations demonstrate that p-bits are not tied to magnetism. FeFET p-bits based on few-domain Hf$$P(m_i=+1)=\frac{1}{1+e^{-2I_i}},\qquad I_i=\beta\sum_j W_{ij}m_j,$$6Zr$$P(m_i=+1)=\frac{1}{1+e^{-2I_i}},\qquad I_i=\beta\sum_j W_{ij}m_j,$$7O$$P(m_i=+1)=\frac{1}{1+e^{-2I_i}},\qquad I_i=\beta\sum_j W_{ij}m_j,$$8 use thermal-noise-induced lattice vibrations to produce tunable current fluctuations and a sigmoid-like “p-curve”; Luo et al. implemented a true-random p-bit with a 1FeFET+1R cell and analyzed how domain number, coupling strength, parameter spread, temperature, and viscosity shape stochasticity (Luo et al., 2023). A manganite nanowire p-bit based on an LPCMO electronic phase-separation domain exhibited telegraph noise between ferromagnetic-metallic and charge-ordered-insulating states, with a sigmoid $$P(m_i=+1)=\frac{1}{1+e^{-2I_i}},\qquad I_i=\beta\sum_j W_{ij}m_j,$$9 characterized near $\beta$0 K by $\beta$1 nA and $\beta$2 (Wang et al., 6 Feb 2025). LSMO thin films on twin-textured LaAlO$\beta$3 showed both clocked binary switching and unclocked multi-bit switching near an electrically triggered metal-insulator transition, indicating that the same material system can support qualitatively different stochastic regimes (Bhaduri et al., 26 Mar 2025).

Organic and memristive platforms extend the concept further. A polymer memristor based on oxidized pTPAC$\beta$4DTP used stochastic resistance fluctuations, a voltage divider, and a comparator to realize a logistic transfer function

$\beta$5

while pulsed $\beta$6-$\beta$7 ensembles were used to compute discrete Shannon entropy, whose peak near $\beta$8 V coincided with maximal variability in the memristor voltage drop (Foulger et al., 22 Sep 2025). Across these implementations, the defining feature remains unchanged: a controllable stochastic binary response arising from device physics rather than from a software PRNG.

4. Computational roles and applications

One of the earliest and most distinctive p-bit applications is invertible logic. In reciprocal p-circuits, a Boolean function is encoded so that truth-table-consistent states correspond to low-energy configurations. A 3-p-bit AND gate and a 5-p-bit full adder were demonstrated on FPGA, with the latter reduced from an earlier 14-p-bit design via Gram–Schmidt orthogonalization. The same framework was cascaded into ripple-carry adders and used to solve a small Subset Sum Problem instance for $\beta$9 with target $W_{ij}$0, where the correct subset appeared as the highest peak in a histogram over $W_{ij}$1 samples (Pervaiz et al., 2017).

Integer factorization has been a recurrent benchmark. In the FeFET work, invertible logic circuits built from IAND gates and full adders were used for 2-bit×2-bit factorization of $W_{ij}$2, where the correct assignments $W_{ij}$3 and $W_{ij}$4 had the highest steady-state probabilities of about $W_{ij}$5. For $W_{ij}$6, MATLAB simulations over $W_{ij}$7 update cycles showed a nonmonotonic dependence of success on stochasticity: $W_{ij}$8 gave about $W_{ij}$9 accuracy, $$m_i \leftarrow \operatorname{sgn}\!\bigl[\tanh(I_i)+r_i\bigr],$$0 about $$m_i \leftarrow \operatorname{sgn}\!\bigl[\tanh(I_i)+r_i\bigr],$$1, $$m_i \leftarrow \operatorname{sgn}\!\bigl[\tanh(I_i)+r_i\bigr],$$2 about $$m_i \leftarrow \operatorname{sgn}\!\bigl[\tanh(I_i)+r_i\bigr],$$3, and $$m_i \leftarrow \operatorname{sgn}\!\bigl[\tanh(I_i)+r_i\bigr],$$4 about $$m_i \leftarrow \operatorname{sgn}\!\bigl[\tanh(I_i)+r_i\bigr],$$5, indicating an optimal stochastic regime rather than monotonic improvement with either more or less noise (Luo et al., 2023).

Optimization and probabilistic machine learning occupy a larger application class. P-computers have been used for Bayesian networks, 0–1 knapsack MCMC, Ising-model optimization, MAX-CUT, Boltzmann machines, and deep Boltzmann machines. FPGA-based p-computers reached $$m_i \leftarrow \operatorname{sgn}\!\bigl[\tanh(I_i)+r_i\bigr],$$6 MSamples/s for moderately sized Bayesian networks and solved a $$m_i \leftarrow \operatorname{sgn}\!\bigl[\tanh(I_i)+r_i\bigr],$$7 MAX-CUT instance in less than $$m_i \leftarrow \operatorname{sgn}\!\bigl[\tanh(I_i)+r_i\bigr],$$8 ms in the reported prototype settings (Kaiser et al., 2021). A full-stack review further described sparse deep Boltzmann machine training on full MNIST using $$m_i \leftarrow \operatorname{sgn}\!\bigl[\tanh(I_i)+r_i\bigr],$$9 p-bits and variational many-body ground-state calculations for a 12-spin Heisenberg chain using an RBM ansatz mapped to p-bit hardware (Chowdhury et al., 2023).

Quantum simulation is possible for the sign-problem-free, or stoquastic, subset of quantum many-body models. Using the Suzuki–Trotter decomposition, a $r_i$0-dimensional quantum Hamiltonian is mapped to a $r_i$1-dimensional classical Ising model, which can then be sampled by a p-bit network. Room-temperature MTJ-based p-circuits were proposed as hardware accelerators for such Quantum Monte Carlo workloads, and later p-computer studies emulated a 250-qubit transverse-field Ising model using $r_i$2 replicas, i.e. $r_i$3 p-bits, reproducing spin-spin correlations with $r_i$4 samples (Camsari et al., 2018, Kaiser et al., 2021).

Directed inference and stochastic sensing form another branch. In a toy pedigree-style Bayesian network, operationally stable manganite p-bits were shown in simulation to suppress relative inference error strongly: with $r_i$5, corresponding to the experimentally observed $r_i$6, the relative error $r_i$7 remained below about $r_i$8 even for deep networks, whereas larger $r_i$9 produced much larger and more erratic errors (Wang et al., 6 Feb 2025). Separately, ensembles of p-bits have been proposed as precision sensors for magnetic field, temperature, and timekeeping, with signal-to-noise ratio scaling as $[-1,+1]$0 and specific detectivity expressions derived from the collective fluctuations of independent thermally activated two-state devices (Liu et al., 2024).

True random-number generation is not ancillary but intrinsic to many p-bit platforms. The manganite nanowire p-bit passed all 12 categories of the NIST Statistical Test Suite on $[-1,+1]$1 raw bits sampled at $[-1,+1]$2 Hz without post-processing (Wang et al., 6 Feb 2025), and LSMO-based p-bits likewise passed NIST randomness tests in the reported supplementary analysis (Bhaduri et al., 26 Mar 2025).

5. Performance metrics, robustness, and scaling

A distinctive contribution of the p-bit literature is the elevation of flips per second to a substrate-independent figure of merit. For autonomous hardware, Borders et al. wrote

$[-1,+1]$3

where $[-1,+1]$4 is the synapse propagation time and $[-1,+1]$5 is the average time between actual flips of one p-bit. By contrast, a sequenced design updating $[-1,+1]$6 neurons in parallel at clock period $[-1,+1]$7 is limited by

$[-1,+1]$8

Using $[-1,+1]$9 ps and $\{0,1\}$0, an autonomous machine with $\{0,1\}$1 p-bits was projected to reach $\{0,1\}$2 flips/s. With an energy cost $\{0,1\}$3 fJ/flip, the corresponding $\{0,1\}$4 Pflips/s machine was projected at $\{0,1\}$5 W (Sutton et al., 2019).

The broader full-stack literature places these projections against existing emulators and device estimates. Reviews reported FPGA emulators at about $\{0,1\}$6 flips/s, projected asynchronous spintronic hardware at $\{0,1\}$7 flips/s, fluctuation times of about $\{0,1\}$8 ns for spintronic p-bits, and a path toward more than $\{0,1\}$9 p-bits per chip by leveraging MRAM-compatible integration; the same review cited a Quantum Monte Carlo acceleration of more than $s_i\in\{0,1\}$00 over optimized C++ CPU code for a 2D frustrated Ising case (Chowdhury et al., 2023). Experimental CMOS-integrated cells remain much slower than these asymptotic projections, but they establish feasibility and expose concrete circuit bottlenecks such as MTJ dwell time, threshold-centering, output swing, and unwanted spin-transfer torque (Zhang et al., 6 Apr 2026, Yoon et al., 15 Apr 2026).

Robustness has been analyzed at both device and array levels. For low-energy-barrier nanomagnets, reasonable thickness and lateral-dimension variations caused only small changes in the probability-versus-current curve, and the spread was reduced further by increasing spin polarization (Drobitch et al., 2019). For operational stability under repeated use, the manganite nanowire device quantified the standard deviation of repeatedly measured probability values across nine current setpoints and 100 repetitions per setpoint; the largest observed $s_i\in\{0,1\}$01, expressed as a fraction, was below $s_i\in\{0,1\}$02 (Wang et al., 6 Feb 2025).

Large-array nonuniformity introduces a different challenge: each physical p-bit may have a different gain and offset. A recent compensation framework modeled these deviations through two parameters, $s_i\in\{0,1\}$03 and $s_i\in\{0,1\}$04, in

$s_i\in\{0,1\}$05

It then rederived compensated weights and biases so that a nonideal array emulates an ideal one without retraining the problem weights. The prerequisite extraction of $s_i\in\{0,1\}$06 and $s_i\in\{0,1\}$07 was performed automatically via Boltzmann-machine-style learning on a 3D ferromagnetic probe Hamiltonian, and the resulting extraction-plus-compensation pipeline restored near-ideal behavior on both a 16-city TSP and a 21-bit integer-factorization benchmark (Zhang et al., 2024).

The main scaling lesson is therefore twofold. First, p-bit performance is increasingly judged by probabilistic throughput rather than by deterministic clock rate. Second, large-scale practicality depends not only on fast stochastic primitives but also on calibrated synapse time, device-to-device uniformity, and compensation methods that preserve the target distribution in the presence of analog variability.

6. Extensions, misconceptions, and terminological ambiguity

The binary p-bit has been generalized to higher-state stochastic units. In a K-state formulation, each node occupies one of $s_i\in\{0,1\}$08 orthonormal basis vectors, and the update is decomposed into a binary “stay versus flip” decision plus a uniform selection among the other $s_i\in\{0,1\}$09 states. The proposed engine requires $s_i\in\{0,1\}$10 traditional two-state p-bits plus one shared multi-state p-bit for an $s_i\in\{0,1\}$11-node K-state system. For Max-3-Cut on a 30-node graph, this native 3-state engine used 30 two-state p-bits plus 1 multi-state p-bit rather than the 90 binary p-bits required by a graph-reduction approach, while achieving the same reported distribution of cut values with a peak around $s_i\in\{0,1\}$12; Max-4-Cut was also demonstrated using a linear anneal of $s_i\in\{0,1\}$13 from $s_i\in\{0,1\}$14 to $s_i\in\{0,1\}$15 (Bashar et al., 2024). This suggests that the p-bit concept is best understood as a stochastic computational primitive rather than as a permanently binary device family.

A recurrent misconception is that correct p-bit operation always requires strict sequential updating. Reciprocal Boltzmann sampling often does require one-at-a-time Gibbs updates, as in FPGA tiles, but autonomous sequencerless designs have also been shown to preserve high-fidelity sampling when simultaneous flips are made sufficiently unlikely by a small intrinsic flip parameter (Pervaiz et al., 2017, Sutton et al., 2019). Another misconception is that p-bits are inherently magnetic. The nanomagnetic route is prominent, but the literature explicitly includes digital CMOS realizations and argues that any fluctuating resistor combined with a transistor can serve as a p-bit substrate (Camsari et al., 2018).

There is also a genuine terminological ambiguity. In a separate line of work on Constructible Duality logic, “p-bits” denote 4-valued paraconsistent truth values, represented as elements of a product Heyting algebra and taking the crisp values $s_i\in\{0,1\}$16, $s_i\in\{0,1\}$17, $s_i\in\{0,1\}$18, and $s_i\in\{0,1\}$19 for true, false, both, and neither. Those p-bits are used to ground probabilistic reasoning, probabilistic programming, and concept formation in the OpenCog framework (Goertzel, 2020). This usage is mathematically and semantically distinct from the stochastic-hardware p-bit, despite the shared name.

Taken together, these extensions and ambiguities delineate the current scope of the term. In contemporary probabilistic computing, the p-bit is primarily a tunable stochastic neuron whose physical realizations and network architectures are engineered to exploit noise constructively. Its generalizations to K-state engines, its deployment across diverse material platforms, and the coexistence of a separate logical meaning all indicate that the concept is still expanding, but its core identity remains the controlled stochastic binary update law that enables hardware-native sampling and inference.