Coherent Conveyor-Mode Spin Qubit Shuttling

• The paper demonstrates that dynamic electrostatic control in conveyor-mode shuttling achieves high-fidelity (<99.99% per hop) spin qubit transport across quantum dot arrays.
• Methodologies like four-phase and eight-phase conveyors, combined with motional narrowing, effectively mitigate Overhauser noise and nonadiabatic errors.
• Error dynamics, including Landau–Zener transitions and variable valley splitting, are addressed via trajectory optimization and advanced signal modulation for scalable architectures.

Coherent conveyor-mode spin qubit shuttling is a key paradigm for transporting spin-based quantum information across mesoscopic and macroscopic distances within semiconductor quantum processors. The approach relies on dynamically translating the minimum of a confining electrostatic potential—either smoothly (traveling-wave “conveyor belt”) or discretely (bucket-brigade mode)—so as to move an individual electron spin or encoded spin state through an array of quantum dots while preserving phase coherence. This technique is fundamentally motivated by the need for high-fidelity, reconfigurable, mid-range quantum connectivity in scalable qubit architectures.

1. Physical Principles and Device Architectures

Conveyor-mode shuttling implements dynamically controlled electron transport via time-dependent gate voltages that shape and move the quantum dot potential. In the canonical “four-phase” conveyor, the potential minimum is propagated along a one-dimensional electron channel (1DEC) using four global, phase-shifted AC signals, requiring only a constant number of control lines irrespective of channel length (Seidler et al., 2021, Struck et al., 2023). The device architecture typically consists of an interleaved gate array, often with grouping that permits global addressing—for example, every fourth gate tied together—compatible with industrial Si/SiGe or SiMOS fabrication.

The electrostatic waveform is generally of the form

$$V_{n}(t) = V_{n}^{\text{DC}} - A \sin(2\pi f t - \phi_{n}),$$

with $\phi_{n}$ staggered to produce a smoothly traveling potential minimum at velocity $v = \lambda f$, where $\lambda$ is the gate pitch (Smet et al., 11 Jun 2024). Variants include "eight-phase" (two-tone) conveyors to suppress spurious local minima and increase robustness against disorder (Smet et al., 11 Jun 2024). The moving dot maintains strong transverse confinement and a sizeable orbital gap ($\Delta E \sim 1$–$10$ meV), crucial for adiabaticity and Landau–Zener error suppression (Sokolov et al., 8 Oct 2025).

2. Quantum Dynamics, Error Mechanisms, and Motional Narrowing

During conveyor-mode shuttling, the electron spin is subjected to several decoherence channels:

• Magnetic dephasing: For $N < 10^3$ hop operations (typically up to $14~\mu$s), theoretical and experimental results show decay dominated by Overhauser (hyperfine) noise, leading to a singlet return probability $S(t) = A \exp[-(t/T_2^*)^p] + y_0$, with $T_2^* \sim 5~\mu$s $p \sim 1.8$, Gaussian, Overhauser-limited at $B_0\approx 0$ mT.
• Echo-protected regime: Hahn-echo or higher-order dynamical decoupling suppresses low-frequency noise, extending $T_2^{\text{Hahn}}$ up to $84.5$ $\mu$s; echo-protected ensemble coherence length is $$N_{\text{echo}} \sim T_2^{\text{Hahn}} / t_0 \sim 6 \times 10^3$$ dots (Foster et al., 16 Jul 2024).
• Incoherent shuttle errors: For large $N$ ($N \gtrsim 10^3$), additional $N$-dependent errors arise, attributed to incoherent spin-flip channels; the decay becomes steeper than the echo envelope, and is well fit by $S(N) = A \exp[-(N / N^*)^\alpha] + y_0$ with $N^* \sim 1.9 \times 10^4$, $\alpha \sim 0.4$ (Foster et al., 16 Jul 2024).

A central transport metric is the remaining singlet (or coherence) probability after $N$ steps:

$S(N) = S_0 \exp\bigl[-(N/N_\varphi)^p\bigr] + y_0.$

Motional narrowing emerges as an essential protection mechanism: rapid translation through spatially fluctuating Overhauser and $g$-factor environments effectively averages the decoherence, leading to a $T_2^*$ that increases with velocity and shuttling distance (Struck et al., 2023, Volmer et al., 4 Oct 2025). The crossover to motional narrowing can be directly observed as a transition from stepwise (Lindblad-type) to suppression of decoherence rates as $v$ increases (Struck et al., 2023, Sokolov et al., 8 Oct 2025).

3. Quantitative Performance Metrics and Scaling

Experimental and theoretical studies demonstrate the following operational performance:

Parameter	Typical Value / Range	Reference
Per-hop error rate	$\epsilon < 10^{-4}$	(Foster et al., 16 Jul 2024)
Uncorrected error limit	$N^* \sim 10^4$ steps	(Foster et al., 16 Jul 2024)
Shuttle time per hop	$t_0 \approx 14$ ns	(Foster et al., 16 Jul 2024)
Adiabatic tunnel coupling	$t_c \gg 1$ GHz ($\approx 52$ GHz in Si/SiGe)	(Foster et al., 16 Jul 2024)
Static $T_2^*$	$5-10$ $\mu$s (isotopically enriched Si)	(Foster et al., 16 Jul 2024, Smet et al., 11 Jun 2024)
Echo-protected $T_2$	$80-90$ $\mu$s	(Foster et al., 16 Jul 2024, Noiri et al., 2022)
Fidelity over 10 $\mu$m	$>99\%$	(Smet et al., 11 Jun 2024, Struck et al., 2023, Volmer et al., 2023, Volmer et al., 4 Oct 2025)
Scaling with gate pitch	$N_{1/e} \sim T_2^* / t_0$	(Foster et al., 16 Jul 2024)

Sources of infidelity are dominated by: (1) Overhauser magnetic noise at low $N$, (2) valley-state crossings and spin-valley mixing at low valley splitting, and (3) residual charge/disorder-induced orbital errors. Experimental error-per-hop values as low as $\epsilon < 2 \times 10^{-5}$ are measured in isotopically enriched $^{28}$Si (Foster et al., 16 Jul 2024), with per-hop phase-flip probabilities $\sim10^{-4}$–$10^{-5}$ in optimized conveyor arrays (Smet et al., 11 Jun 2024, Volmer et al., 2023).

4. Valley Splitting, Disorder, and Optimized Pathways

A critical constraint for conveyor-mode shuttling in Si/SiGe is the random spatial variation of the conduction-band valley splitting $E_{\text{VS}}$, which arises from Ge-alloy disorder, interface steps, and well-thickness fluctuations. Mapping experiments (Volmer et al., 2023, Volmer et al., 4 Oct 2025) and disorder modeling (Losert et al., 3 May 2024, David et al., 11 Sep 2024, Németh et al., 12 Dec 2024) reveal sub-$\mu$eV to $200~\mu$eV variation on $10$–$20$ nm length scales, with inevitable "hotspots" of low $E_{\text{VS}}$ where Landau–Zener transitions and spin-valley resonances enhance decoherence.

Mitigation strategies include:

• Pre-characterization and Trajectory Optimization: 2D mapping of $E_{\text{VS}}(x, y)$ enables selection of shuttling paths that avoid low-valley-splitting regions (Volmer et al., 2023, Volmer et al., 4 Oct 2025, Losert et al., 3 May 2024).
• Velocity Profile Shaping: Optimizing shuttling trajectories with few-parameter (Fourier) velocity modulation enables error suppression below fault-tolerant thresholds (down to $P_{\text{err}} \sim 10^{-4}$ over $10~\mu$m) without the need for detailed knowledge of disorder minima (David et al., 11 Sep 2024). Slow passage through dangerous regions and quick traversal elsewhere minimizes both Landau–Zener leakage and phase-accumulation errors.
• Heterostructure Engineering: Narrower quantum wells, Ge doping, and engineered interfaces raise the mean $E_{\text{VS}}$, reducing the frequency of dangerous pockets (Losert et al., 3 May 2024).
• Multi- and Two-Dimensional Shuttling: Lateral or omnidirectional shuttling architectures enable detours around valley minima, with simulated fidelities $>99.9\%$ for 2D omnidirectional systems (Németh et al., 12 Dec 2024).

5. Error Dynamics: Landau–Zener Physics, Echo Sequences, and Defect Tolerance

The error dynamics of conveyor-mode shuttling are governed by a combination of adiabatic charge-transfer criteria (Landau–Zener formalism), noise spectral properties, and relaxation processes:

• Landau–Zener transitions: The shuttling process is formalized as a sweep across avoided crossings in the dot spectrum. The nonadiabatic transition probability is $$P_{\text{LZ}} = \exp(-2\pi\Delta^2 / \hbar|\dot{\epsilon}|)$$, where $\Delta$ is the anticrossing gap and $\dot{\epsilon}$ the detuning ramp rate (Ginzel et al., 2020).
• Interference Effects: Multiple traversals induce Landau–Zener–Stückelberg interference; ramp timing and parameter tuning can maximize constructive interference, minimizing residual leakage (Ginzel et al., 2020).
• Spin-echo, Hahn-echo, and CPMG sequences: Inserting mid-shuttle $\pi$-pulses suppresses low-frequency noise, extending coherence lengths and pushing overall errors below $10^{-4}$ (Foster et al., 16 Jul 2024, Smet et al., 11 Jun 2024).
• Defect tolerance: Sparse charged-defect densities up to $n_d \sim 10^{14}$ cm$^{-3}$ can be tolerated; higher densities or close proximity to the transport path induce orbital excitations and $g$-factor shifts, but strong radial confinement and high drive amplitude suppress these errors (Ciroth et al., 3 Dec 2025).

Fidelity budgets combine dephasing, phase-flip, and leakage terms, with full density-matrix simulations supporting the experimental claims of multi-micron coherent shuttling (Smet et al., 11 Jun 2024, Struck et al., 2023, Ciroth et al., 3 Dec 2025).

6. Applications and Integration in Scalable Architectures

Coherent conveyor-mode spin qubit shuttling solves several key challenges for large-scale semiconductor quantum computing:

• Quantum Bus Design: The QuBus and similar architectures allow the creation of mid-range quantum interconnects using only four (or a small constant number of) global control signals (Seidler et al., 2021, Escofet et al., 20 Oct 2025). Spin shuttling supports both intra- and inter-module qubit links required for surface-code–based error correction with logical error rates as low as $2 \times 10^{-10}$ per round at code distance $d=21$ (Escofet et al., 20 Oct 2025).
• Sparse Control/Fanout Problem: The control signal count is independent of bus length, facilitating the routing of qubits through dense arrays with minimal wiring complexity (Seidler et al., 2021, Langrock et al., 2022).
• Gate-based Two-Qubit Operations: Shuttling enables coupling between spatially separated spins, with demonstrated controlled-phase (CZ) gate fidelities of $93\%$ and shuttling-driven exchange on/off ratios $>1000$ (Noiri et al., 2022).
• Modularity and Networked Topologies: Conveyor and omnidirectional shuttlers can link 2D qubit plaquettes for all-to-all local connectivity, supporting flexible code layouts and high-throughput error correction (Németh et al., 12 Dec 2024).

Scalability is further enabled by virtual-gate techniques for large arrays (Noiri et al., 2022), integration with quantum register-based computation and syndrome extraction (Escofet et al., 20 Oct 2025), and compatibility with the surface code–motivated architectures (Escofet et al., 20 Oct 2025).

7. Future Directions, Limitations, and Engineering Considerations

Further advances are driven by:

• Materials Engineering: Maximizing valley splitting, minimizing interface disorder, and optimizing dot geometry and quantum well composition are crucial for error suppression (Losert et al., 3 May 2024, Volmer et al., 4 Oct 2025).
• Active Pathway Selection and Real-time Calibration: In situ mapping of disorder and real-time trajectory optimization—via few-parameter waveform tuning—are anticipated to become standard (David et al., 11 Sep 2024, Volmer et al., 2023).
• Omnidirectional/2D Shuttling: Full 2D conveyor architectures show promise for circumventing valley disorder and enabling complex qubit routing; simulations predict $>99.9\%$ fidelity for $10~\mu$m shuttles with practical gate layouts and RF requirements (Németh et al., 12 Dec 2024).
• Error Correction and Logical Operation Integration: Quantitative studies of logical error rates considering all relevant noise channels confirm the suitability of conveyor-mode shuttling for surface code architectures (Escofet et al., 20 Oct 2025).

Limitations remain in the form of rare but spatially inevitable disorder-induced decoherence events, constraints from charge noise, and potential crosstalk between densely packed bus lines. However, with enhancements in heterostructure quality, device yield, and control electronics, conveyor-mode shuttling is positioned as a cornerstone technology for mid- and large-scale silicon spin-qubit processors (Foster et al., 16 Jul 2024, Smet et al., 11 Jun 2024).