Single Chalcogenide X-point Memory (SXM)

• SXM is a two-terminal memory concept where a single amorphous chalcogenide alloy performs both storage and selector functions through polarity-dependent ovonic threshold switching.
• The graded band gap (GBG) model explains the internal asymmetry by showing that programming creates a polarity-imprinted gradient in localized electronic states, as validated by electrical measurements, TCAD simulations, and DFT calculations.
• Device performance, including the memory window (ΔV_T), is governed by design parameters like temperature, film thickness, and alloy composition, enabling optimization for dense 3D integration.

Searching arXiv for the specified paper and closely related work on SXM and polarity-dependent ovonic threshold switching. Single-chalcogenide X-point Memory (SXM) is a two-terminal memory concept in which a single film of an amorphous chalcogenide alloy serves as both a memory and selector unit. In the formulation developed by Fantini et al., SXM exploits the observation that the ovonic threshold switching voltage $V_T$ depends on the polarity of the applied field, so that the polarity sequence of the immediately preceding write pulse determines whether a subsequent read encounters a lower or higher threshold voltage. The resulting device combines self-selection and 1-bit storage in a single chalcogenide layer, and its operation is described microscopically by a Graded Band Gap (GBG) model supported by electrical measurements, TCAD simulations, and DFT calculations (Fantini et al., 16 Aug 2025).

1. Device architecture and dual functionality

The core of an SXM cell is a sub-20 nm-thick layer of an amorphous chalcogenide alloy, such as Ge–As–Se, sandwiched between two inert electrodes. In a cross-point array, rows and columns of metal wires address each cell via two terminals, with no diode or transistor. Below a polarity-dependent threshold voltage $V_T$, the chalcogenide remains in a high-resistance OFF state with only a small leakage current of $<100\ \mathrm{nA}$. Above $V_T$, it abruptly switches into a low-resistance ON state by ovonic threshold switching. The same structure also stores information because the $V_T$ observed on a read pulse depends on the polarity sequence of the immediately preceding program pulse, yielding two distinct thresholds, $V_{T,\text{LOW}}$ and $V_{T,\text{HIGH}}$, that encode a binary bit (Fantini et al., 16 Aug 2025).

The operational cycle is polarity-sequenced. A program SET pulse, positive or negative, establishes a graded defect profile in the film. A read at identical polarity sees the lower threshold $V_{T,\text{LOW}}$, corresponding to ON $=$ “1”. A read at opposite polarity sees the higher threshold $V_{T,\text{HIGH}}$, corresponding to OFF $V_T$0 “0”. A common misconception is to treat the selector and memory roles as necessarily requiring separate devices or a selector stack; SXM is explicitly defined by the use of a single chalcogenide film that performs both functions. This unification is central to its relevance for cross-point arrays and for dense 3D integration.

2. Microscopic origin of polarity-dependent threshold switching

The key microscopic observation is that programming produces a built-in asymmetry in the chalcogenide film. At the programming anode, described as the electron-injecting side, a high density of conduction-band electrons drives irreversible red-shifts of certain empty localized states toward the valence band. These states become easier to fill and reduce the activation energy for hole injection during later reads of the same polarity. At the programming cathode, described as the high-field side, the strong electric field irreversibly removes or “cleans out” some localized gap states, increasing the activation energy for hole injection when that side becomes the new anode on a reversed read (Fantini et al., 16 Aug 2025).

This asymmetry directly explains the polarity dependence of $V_T$1. When the device is read with the same polarity used for programming, holes tunnel in at the “soft” anode, where the barrier is lower, so the threshold voltage is reduced. When the polarity is reversed, holes must cross the “hardened” side, where the barrier is higher, and the threshold voltage increases. The interpretation is therefore not a purely interfacial account in the narrow sense of an unchanged bulk with asymmetric contacts; rather, the device is described as retaining a polarity-imprinted internal profile of localized electronic states across the film. This suggests that the memory window arises from a persistent internal state of the amorphous layer rather than from a transient readout artifact.

3. Graded Band Gap model

The GBG model attributes the SXM programming window to a spatially varying profile of localized trap states and effective band edges $V_T$2 across the film thickness $V_T$3. After a programming pulse of polarity “+”, the anode side at $V_T$4 is rich in red-shifted traps, while the cathode side at $V_T$5 is trap-depleted. The model represents the spatial variation of the gap by the linear approximation

$V_T$6

where $V_T$7. A positive $V_T$8 corresponds to a wider gap at the cathode after a “+” program pulse (Fantini et al., 16 Aug 2025).

The localized state distribution is modeled as

$V_T$9

with the trap-band center

$<100\ \mathrm{nA}$0

where $<100\ \mathrm{nA}$1 is the local valence-band edge and $<100\ \mathrm{nA}$2–0.5. Sub-threshold conduction is captured by a Tunneling-Assisted Poole-Frenkel law,

$<100\ \mathrm{nA}$3

where $<100\ \mathrm{nA}$4 is the local injection barrier and $<100\ \mathrm{nA}$5 the electric field. Threshold switching is then triggered by a bipolar impact-ionization-avalanche process with coefficient

$<100\ \mathrm{nA}$6

Because $<100\ \mathrm{nA}$7 differs at the two sides, the critical field $<100\ \mathrm{nA}$8, and hence $<100\ \mathrm{nA}$9, is lower when holes avalanche from the side with the smaller local gap and higher when the film is read in reverse, reproducing

$V_T$0

Within this framework, SXM memory is not modeled as conventional structural phase storage. The persistent state variable is instead the graded distribution of localized states and effective gap values. A plausible implication is that the device memory window is fundamentally coupled to defect energetics and carrier injection asymmetry rather than to crystallization.

4. Numerical and electronic-structure support

The TCAD implementation reported for the GBG model uses a 1D film of thickness $V_T$1 between ideal ohmic contacts. The trap density is set to $V_T$2, with Gaussian width $V_T$3. Hole transport is described by trap-to-trap hopping with Poole-Frenkel field dependence, while electrons are assigned higher mobility. The impact-ionization parameters $V_T$4 and $V_T$5 are chosen to match the experimental $V_T$6 characteristics (Fantini et al., 16 Aug 2025).

The reported agreement with experiment is quantitative. At $V_T$7, the measured values are approximately $V_T$8 for SET, identified with low $V_T$9, and $V_T$0 for RESET, identified with high $V_T$1. The TCAD curves match these within $V_T$2. As temperature rises to $V_T$3, both threshold voltages drop by about $V_T$4, and this behavior is reproduced through the thermally activated $V_T$5. The field-dependent analysis also shows that the effective avalanche coefficient slope is reduced when the device is read in opposite polarity, consistent with the higher threshold.

The DFT molecular-dynamics results provide atomistic support for the two-sided asymmetry. Four independent 300-atom Ge$V_T$6As$V_T$7Se$V_T$8 models are quenched from the melt. In each model, the highest-localized empty state, identified as the LUMO, lies about $V_T$9–$V_{T,\text{LOW}}$0 below the conduction band. Injecting 4 extra electrons and relaxing the structure produces a polaronic red-shift of that LUMO by about $V_{T,\text{LOW}}$1 toward the valence edge, and the shift is irreversible on electron removal. Applying a uniform field $V_{T,\text{LOW}}$2 to clamped ions and relaxing leads to removal or blue-shift of some gap states by $V_{T,\text{LOW}}$3–$V_{T,\text{LOW}}$4 in 2 of 4 models. A slow quench under $V_{T,\text{LOW}}$5 likewise yields a net widening of the gap on final relaxation. Together, these results support the anode–cathode asymmetry posited by the GBG model.

5. Dependence on temperature, thickness, and composition

The SXM programming window depends systematically on temperature, film thickness, and alloy composition. For temperature, the reported dependence is

$V_{T,\text{LOW}}$6

Both experiment and TCAD show that increasing temperature lowers the threshold voltages, while preserving the qualitative distinction between $V_{T,\text{LOW}}$7 and $V_{T,\text{LOW}}$8 (Fantini et al., 16 Aug 2025).

For thickness, the memory window

$V_{T,\text{LOW}}$9

scales roughly linearly with $V_{T,\text{HIGH}}$0,

$V_{T,\text{HIGH}}$1

Thinner films of $V_{T,\text{HIGH}}$2 reduce $V_{T,\text{HIGH}}$3 below $V_{T,\text{HIGH}}$4, making margin-setting more difficult. This establishes a direct trade-off between aggressive vertical scaling and read-margin robustness.

For composition, Fantini et al. express the alloy ionicity as $V_{T,\text{HIGH}}$5 and report

$V_{T,\text{HIGH}}$6

Alloys with higher ionicity form stronger polar As–Se and Ge–Se bonds and exhibit a larger field-induced gap gradient $V_{T,\text{HIGH}}$7, hence a larger memory window. In the logic of the GBG model, chemistry enters device behavior through its control over the stability and field response of localized states. This suggests that material optimization for SXM is inseparable from electronic-structure engineering.

6. Design implications, scaling, and interpretive boundaries

The reported device implications follow directly from the GBG framework. Dimension scaling requires a compromise between lateral packing density, which favors thinner films, and sufficiently large $V_{T,\text{HIGH}}$8, which favors thicker films. The indicated target is $V_{T,\text{HIGH}}$9–20 nm for 20 nm node arrays. Alloy optimization favors higher ionicity, for example by raising Se content, up to the point where crystallization temperature and thermal stability remain safe for endurance. Switching speed is linked to the local defect transformations at anode and cathode, which are identified as the basis for sub-ns SET/RESET in SXM; thinner films further reduce $V_{T,\text{LOW}}$0 and therefore RC delay and switching delay. The GBG model also suggests that reducing trap density $V_{T,\text{LOW}}$1 or engineering sharper band-edge steps via deposition or sub-layer doping lowers the required avalanche field and cuts write energy. Because no additional selector stack is needed, single-layer SXM cells can be built into 3D tiers with $V_{T,\text{LOW}}$2 half-pitch, with terabit-scale 3D memory identified as a possible outcome (Fantini et al., 16 Aug 2025).

Interpretively, the model places the central explanatory weight on a polarity-imprinted gradient of localized states and effective band gap. That position excludes simpler descriptions in which threshold switching is polarity-independent and memory is stored elsewhere in the stack. At the same time, the evidence presented is specifically the combination of electrical measurements, 1D TCAD, and DFT molecular dynamics; the reported conclusions therefore define a microscopic model rather than an exhaustive closure of all possible mechanisms. Within that evidentiary scope, SXM is characterized as a chalcogenide memory-selector architecture whose essential feature is the retention of a graded electronic-state profile after programming, enabling the same film to self-select and to store one bit.