DRAMA: Commodity DRAM as CAM

• DRAMA is Commodity DRAM-based Content Addressable Memory that repurposes existing DRAM architecture for fast parallel search using binary, ternary, and approximate matching.
• It converts data storage from row-major to column-major order, turning DRAM bitlines into matchlines and encoding queries via DRAM row addresses for bit-serial XNOR operations.
• DRAMA delivers notable performance improvements in genome classification, achieving higher throughput and lower power consumption compared to conventional CAM approaches.

DRAMA, short for Commodity DRAM based Content Addressable Memory, is a technique for implementing content addressable memory functionality directly in unmodified commodity DRAM. It was proposed to address a classic limitation of conventional CAMs: although CAMs provide fast parallel search over large datasets, they incur high silicon-area overhead and power consumption and therefore scale poorly. DRAMA reuses DRAM’s existing structure and timing behavior to support binary CAM, ternary CAM (TCAM), and approximate/similarity search, while preserving the density and low cost of commodity DRAM (Yavits, 2023).

1. Problem setting and architectural premise

Content addressable memories are attractive because they support fast parallel search on large datasets. The difficulty, as formulated by DRAMA, is that conventional CAM implementations compare unfavorably with RAM in area overhead, power consumption, and scalability. DRAMA addresses this by showing that CAM-like behavior can be realized inside ordinary DRAM chips without modifying the chips themselves, provided that data layout and command interpretation are changed appropriately (Yavits, 2023).

At a high level, DRAMA converts DRAM into a search structure by storing datawords in column-major fashion rather than row-major form. Under this organization, DRAM bitlines become matchlines and wordlines become searchlines. Each CAM bit is represented by two 1T1C DRAM cells of the same bit column, with the data bit stored together with its complement. This eliminates the need to add explicit matching logic inside the DRAM chip. A plausible implication is that the proposal derives its density advantage from reusing the native DRAM read path rather than introducing a dedicated CAM cell array.

2. Data representation and query injection

DRAMA’s compare mechanism is explicitly bit-serial. The key observation is that the search pattern is not injected through the data bus. Instead, the query is coded in DRAM row addresses. Only one searchline is active at a time, so an $m$-bit match is accumulated across a sequence of single-bit compares:

$$\text{Match} = \bigwedge_{i=1}^{m} (query_i == dataword_i)$$

where $==$ denotes bitwise XNOR (Yavits, 2023).

The address encoding rule is simple and central to the design. A query bit of 0 causes DRAMA to open an even row, while a query bit of 1 causes it to open the corresponding odd row. Because each logical bit is stored together with its complement in paired rows, selecting one or the other row effectively injects the query into the sense path. This arrangement is what allows the paper to treat comparison as an address-driven variant of ordinary DRAM activation rather than as a separate logic operation.

This organization is also the basis for DRAMA’s support of multiple CAM modes. Binary matching is obtained directly from the bit-serial XNOR process; ternary matching uses a special encoding of “don’t care” states; approximate matching reuses the same primitives together with bulk logic. The architecture therefore relies less on new circuitry than on a reinterpretation of DRAM’s row structure and timing semantics.

3. Single-bit comparison as a DRAM read

The paper’s most important technical claim is that a single-bit compare (XNOR) in DRAMA is identical to a regular DRAM read (Yavits, 2023). The compare cycle begins with PRE, which precharges the matchline to $V_{DD}/2$, leaves the sense amplifier disabled, and sets the searchlines to their negated state. An ACT command then asserts the row corresponding to the query bit.

During charge sharing, the direction of charge flow encodes match or mismatch. If the stored bit matches the query bit, charge flows from the selected 1T1C cell to the matchline and raises it to $V_{DD}/2 + \delta$. If the stored bit mismatches the query bit, charge flows in the opposite direction and the matchline drops to $V_{DD}/2 - \delta$. Once the sense amplifier is enabled, it amplifies the deviation and resolves the matchline to full logic 1 for a match or 0 for a mismatch. The selected cell capacitor is restored at the same time: fully charged on match, fully discharged on mismatch.

This behavior is significant because it places the compare primitive inside ordinary DRAM analog operation. DRAMA does not emulate XNOR in software and does not add a dedicated logic plane; rather, it exploits the fact that the read path already distinguishes between the two complementary stored states. This suggests that the proposal’s novelty lies primarily in mapping search semantics onto existing DRAM physics.

4. Multi-bit exact search and timing-controlled logic

Multi-bit CAM requires accumulation across bit positions. DRAMA performs the per-bit XNOR serially and then combines the partial results with logical accumulation. For this stage, the paper states that AND and OR are realized using nonstandard DRAM timing, specifically by manipulating the timing intervals between PRE and ACT ($t_{RP}$) and between ACT and PRE ($t_{RAS}$) outside standard DRAM specifications (Yavits, 2023).

The mechanism is adopted from row-copy and bulk-logic techniques associated with ComputeDRAM. For row copy, written as $CPY(R_T, R_S)$, the source row $R_S$ is opened with ACT, then PRE is issued, and then ACT opens the target row $$\text{Match} = \bigwedge_{i=1}^{m} (query_i == dataword_i)$$0; the copy depends on shortening $$\text{Match} = \bigwedge_{i=1}^{m} (query_i == dataword_i)$$1 by interrupting PRE prematurely. For logic $$\text{Match} = \bigwedge_{i=1}^{m} (query_i == dataword_i)$$2, the same command sequence is used with minimal inter-command delays. Because AND and OR are majority-based, one of the three participating rows must be preset: all-zeros for AND and all-ones for OR. The row addresses must also satisfy additional constraints.

These timing-controlled operations are used to construct both NAND CAM and NOR CAM. In the NAND flow, a running match result is stored in a row $$\text{Match} = \bigwedge_{i=1}^{m} (query_i == dataword_i)$$3, intermediate XNOR outputs are copied into $$\text{Match} = \bigwedge_{i=1}^{m} (query_i == dataword_i)$$4, and the final state is accumulated using AND. In the NOR variant, the query is inverted, AND is replaced by OR, and the final result is inverted as well, so a match is signaled by 0 rather than 1. Functionally, both organizations implement multi-bit exact search, but they differ in polarity and accumulation logic.

A practical consequence is that DRAMA depends not only on commodity DRAM devices but also on a controller capable of issuing nonstandard timing patterns. The DRAM chips remain unmodified, but system integration is not completely transparent.

5. TCAM semantics and approximate search

DRAMA extends beyond exact binary matching to TCAM and approximate/similarity search. For ternary operation, the key requirement is a representation of “don’t care” bits that does not affect the accumulated compare result. In NAND-based TCAM, the paper encodes don’t-care as 11; in NOR-based TCAM, it uses 00 (Yavits, 2023).

Under that encoding, charge sharing pulls the matchline toward either $$\text{Match} = \bigwedge_{i=1}^{m} (query_i == dataword_i)$$5 or $$\text{Match} = \bigwedge_{i=1}^{m} (query_i == dataword_i)$$6 regardless of whether the query bit is 01 or 10, so the row-local compare leaves the accumulated multi-bit result unchanged. In the paper’s notation,

$$\text{Match} = \bigwedge_{i=1}^{m} (query_i == dataword_i)$$7

and the same identity holds for mismatch propagation. The ternary extension is therefore not implemented by adding a new comparison primitive; it is achieved by selecting a data encoding whose electrical effect is neutral under the accumulation rule.

The paper further extends DRAMA to approximate search, specifically similarity search under a Hamming-distance tolerance. A stored reference dataword is considered a match if its Hamming distance from the query is below a threshold. The concrete example given is a tolerance of 1, implemented using the same NAND-compare logic together with bulk logic operations. This is especially relevant to genome analysis, where exact matching may be too strict. This suggests that DRAMA is best understood not merely as a binary CAM emulation scheme, but as a broader in-DRAM search substrate supporting exact, ternary, and bounded-error matching.

6. Genome classification mapping and empirical evaluation

A major application examined in the paper is bacterial genome classification. The reference database is stored in DRAMA in column-major form, with multiple kmers per column. DNA bases are represented using one-hot encoding:

• $$\text{Match} = \bigwedge_{i=1}^{m} (query_i == dataword_i)$$8
• $$\text{Match} = \bigwedge_{i=1}^{m} (query_i == dataword_i)$$9
• $==$0
• $==$1

The paper notes that this one-hot representation uses the same number of cells as the basic two-cell-per-base representation, but it enables a single DRAM read per DNA base compare, because only one of the four rows storing a base is activated during each compare (Yavits, 2023).

Species-specific reference kmers are mapped to known DRAM column groups. After search, the CPU fetches the result and infers the final taxon from the column address of the matching data item. This mapping makes classification a direct consequence of the search result’s physical location in memory, rather than requiring a separate associative metadata structure.

In evaluation, DRAMA is compared against a CPU baseline, Sieve, and DASH-CAM. On bacterial DNA classification, the paper reports that DRAMA achieves 3.6 times higher performance and 19.6 times lower power consumption than DASH-CAM, identified in the paper as the state-of-the-art CMOS CAM-based genome classification accelerator (Yavits, 2023). The paper also states that Sieve slightly outperforms DRAMA because Sieve performs matching in hardware, but DRAMA still delivers strong throughput and better scalability without modifying the DRAM chip.

7. System requirements, refresh behavior, and broader significance

DRAMA is designed for use with an external memory controller that supports user-configurable DRAM timing. This requirement is important: although the DRAM chips are unmodified commodity devices, the controller may need modification to issue the nonstandard timing sequences required for row copy and bulk logic (Yavits, 2023).

The paper also discusses refresh behavior during repeated compare operations. During compare cycles, matching bits are refreshed as part of the read-restore process. Because compare latency is on the order of less than 200 ns while refresh intervals are around 64 ms, the paper argues that every bit is likely to be exercised over a refresh interval. If some bits become “sticky,” the proposed mitigation is to alternate NAND and NOR CAM operations so that a bit that fails to match under one polarity will match under the other. When compare operations are not underway, ordinary refresh can still be applied.

The broader significance of DRAMA lies in the claim that standard DRAM reads already perform bitwise compare behavior, and that this primitive can be lifted into multi-bit exact search, TCAM, and approximate search by exploiting data layout and timing-controlled bulk logic. This does not make DRAM a conventional CAM in cell design or interface semantics. Instead, it reinterprets commodity DRAM as a high-density searchable memory substrate. A plausible implication is that DRAMA’s contribution is as much architectural as circuit-level: it redefines how existing memory hardware can be used, rather than proposing a new memory technology.