Analog ReRAM Neuromorphic Circuits

• Analog ReRAM neuromorphic circuits are compute-in-memory architectures that exploit ReRAM’s analog switching properties for efficient neural operations and multi-level weight encoding.
• They use frequency-multiplexed analog weighting, bulk switching, and digital-assisted programming to achieve up to 8-bit resolution per device, reducing energy consumption and area footprint.
• Robust circuit designs leverage differential encoding, calibration, and fault-tolerance strategies to mitigate variability and improve overall performance and reliability.

Analog ReRAM neuromorphic circuits are compute-in-memory architectures leveraging the analog switching properties of resistive random-access memory (ReRAM, or RRAM) to implement core neural operations such as vector–matrix multiplication (VMM), synaptic weight storage, and learning functions with extreme area and energy efficiency. These systems exploit device-physics phenomena—including frequency-dependent voltage–current hysteresis and multi-level conductance modulation—to achieve continuous or multi-level weight representation, overcoming the fundamental 1-bit per device limit of conventional filamentary memristors. This article presents the device mechanisms, architectural concepts, circuit schemes, defect tolerance strategies, and quantitative performance of such analog ReRAM neuromorphic circuits, linking physical models to practical system implementation, and addressing design trade-offs and current challenges.

1. Physical Mechanisms for Analog Weight Encoding in ReRAM

Metal-oxide ReRAM devices are two-terminal memristive elements whose instantaneous voltage $v(t)$ and current $i(t)$ obey a coupled system: $v(t) = R(x,i)\,i(t),\quad \dot x = f(x, i)$ where $x$ is a dynamic internal state (e.g., filament geometry or defect density). Under DC or slowly varying bias, a device typically switches between a low-resistance 'ON' and high-resistance 'OFF' state. However, in the analog operating regime, frequency-dependent v–i plane hysteresis is exploited: the area and branch separation of the ‘pinched’ hysteresis loop, as well as the effective ON/OFF conductances $G_{\text{ON}}, G_{\text{OFF}}$, can be tuned by the excitation frequency. The empirical dependence can be modeled as

$$G_{\text{ON}}(f) = G_\infty + (G_0 - G_\infty)\exp(-f/f_c)$$

with similar forms for $G_{\text{OFF}}(f)$; $f_c$ sets the frequency cut-off for hysteresis. The loop area, proportional to energy dissipation per cycle, drops off above $f_A$ as $A_\text{hyst}(f) \propto 1/[1+(f/f_A)^\alpha]$. Operating in the intermediate frequency regime (hundreds of Hz to kHz for typical devices) enables a continuum of effective conductance states for analog weight encoding (Eshraghian et al., 2019).

Extended physical descriptions for analog switching include trap-to-trap tunneling between mid-gap oxygen-vacancy states (in TaOₓ/HfOₓ stacks) and bulk modulation of defect density, as modeled by state-variable rate equations and supported by finite-element solutions of coupled Poisson and heat equations (Falcone et al., 17 Sep 2025, Park et al., 2023). In forming-free bulk tri-layer RRAMs, analog weights are achieved by uniformly modulating the oxygen vacancy profile in an amorphous TiOₓ bulk, producing $>$100 linearly programmable states without filament formation or compliance current (Park et al., 2023).

2. Crossbar Architecture and Multiply–Accumulate Operation

Core analog ReRAM neuromorphic circuits consist of $M \times N$ crossbar arrays, where each intersection is a programmable ReRAM cell with conductance $G_{ij}$ (Goswamy et al., 2015, Eshraghian et al., 2019). Inputs are applied as voltages $V_j$ on word lines, and output currents $I_i$ are summed along bit lines: $I_i(t) = \sum_{j=1}^N G_{ij}(f_j)\, V_j(t)$ Alignment and timing schemes synchronize pulse waveforms across rows for accurate accumulation at peak current time $t^*$. Peak sense amplifier currents effectively realize the neural MAC: $$I_i^{\text{peak}} = \sum_{j=1}^N G_{ij}(f_j) V_{j0}$$ In analog encoding via frequency-multiplexing, each device is statically set to $G_{\text{ON}}$, with the frequency $f_j$ of the input signal selected via a LUT to represent an 8-bit weight (Eshraghian et al., 2019). For bulk/filamentary multi-level devices, weights are mapped directly onto programmable conductance levels, with or without differential encoding (Falcone et al., 17 Sep 2025, Park et al., 2023).

Peripheral analog circuitry (TIA, sample-and-hold, switched-capacitor integrators) performs signal conversion, while phase-aligned arbitrary waveform generators drive the rows with application-specific motifs (e.g., half-sine) for frequency encoding (Eshraghian et al., 2019). Fully analog, stochastic, or digitally-assisted neuron circuits are used for nonlinearity and thresholding (Goswamy et al., 2015, Dang et al., 2024).

3. Multi-Level, Differential, and Analog Weighting Schemes

Early ReRAM-based accelerators struggled with the binary-state limitation, but analog neuromorphic circuits address this with several encoding schemes:

• Frequency-multiplexed analog weighting: Kernel information is partially encoded in the input signal frequency using the device’s nonlinear, frequency-dependent conductance. The mapping $W \mapsto f_W$ is precomputed and stored in a digital LUT. 8-bit resolution per device is demonstrated, yielding area reductions up to $8\times$ compared to bit-slice approaches and power reductions up to $16\times$ over conventional DC-driven binary crossbars, while maintaining full-precision inference accuracy (Eshraghian et al., 2019).
• Bulk switching and compliance-free multi-levels: Forming-free bulk TiOₓ-based RRAM devices, engineered with oxygen-vacancy-rich layers, enable >100 uniformly tunable levels, linear analog switching, and high device-to-device and cycle-to-cycle uniformity. Differential encoding pairs two devices per synapse ($w_{ij} = \alpha[G_{ij}^+ - G_{ij}^-]$) to achieve signed weights and maximize dynamic range, at the cost of doubling array area (Park et al., 2023).
• Trap-to-trap tunneling models: Analytical transport equations connect local vacancy concentration with conductivity, enabling fine-grained simulation and device-level parameter extraction for analog conductance control with high accuracy and stability (Falcone et al., 17 Sep 2025).
• Stochastic and digital analog programming: Relaxation-aware, pulse-width modulated programming using only digital timing controls (fixed voltage and compliance) produces four stable, well-separated conductance levels (2 bits/cell) in HfOₓ 1T1R arrays, with all-peripheral tuning and high array uniformity (Erfanijazi et al., 2023).
• Differential encoding and robustness: All-analog or hybrid schemes leverage differential pairs to suppress common-mode device and defect-induced errors, improving accuracy in the presence of stuck-at faults and nonidealities (Sawal et al., 2024, Fahimi et al., 2021).

4. Circuit-Level Implementation, Nonlinear Activation, and Peripheral Design

Analog neuromorphic systems with ReRAM crossbars critically rely on high-speed, low-noise current-mode input drivers and transimpedance amplifiers for efficient readout and neuron computation (Goswamy et al., 2015). Designs implement regulated-cascode TIAs with feedback and local SAR-controlled bias for process-variation tolerance and minimal input impedance, allowing high-throughput matrix operations at sub-10 fJ/MAC energy and >10× improvement over prior voltage-mode schemes (Goswamy et al., 2015).

For analog nonlinear activation (e.g., Sigmoid, SoftMax), analog comparators and topologically minimal WTA circuits are now feasible. For example, the RACA architecture performs stochastic binarization by exploiting intrinsic ReRAM device noise: the TIA output plus thermal noise is compared to a threshold, and firing probability approximates a hardware-embedded sigmoid, with no digital arithmetic or ADCs employed. SoftMax is implemented by repeating the firing process and empirically estimating the distribution of winner neuron (Dang et al., 2024). This yields an overall 58% energy and 38% area reduction versus 1-bit-ADC baselines at comparable accuracy (96.7% for MNIST after 10 trials).

Peripheral trade-offs include management of phase alignment, frequency-multiplex crosstalk, and area scaling for the LUT and waveform generators (growing as $O(N)$), which are mitigated by time-multiplexing and cluster-sharing schemes (Eshraghian et al., 2019).

5. Fault Tolerance, Variability, and Robustness Strategies

Analog ReRAM circuits are affected by intrinsic device variability (threshold, cycle-to-cycle, and device-to-device conductance), stuck-at faults (stuck-ON/OFF/intermediate), temperature and bias dependence, and layout-induced crosstalk (Sawal et al., 2024, Park et al., 2023, Fahimi et al., 2021, Moro et al., 2022). Comprehensive mitigation methodologies include:

• Differential pair encoding: Faults affecting both branches equally null the net contribution to synaptic current, tolerating up to 10% defect rate before significant accuracy drop; faults which mismatch the “+” and “–” branches strongly degrade inference (Sawal et al., 2024).
• Machine-learning-based post-processing: Defective crossbars can be compensated by training an external multi-layer perceptron to remap the analog output voltages to correct class decisions, restoring accuracy from ~48% (bare circuit) to 85% with no explicit remapping (Sawal et al., 2024).
• Hardware-aware calibration and ex-situ training: Calibrating training to match measured device distributions (conductance variance, time-constants, noise spectra) enables “Neuromorphic Hardware-Calibrated SNNs” to retain >98% of software accuracy (e.g., N-MNIST: 96.8% hardware vs 97.5% software). Heterogeneity in device and neuron/synapse parameters can improve performance for temporal tasks (Moro et al., 2022).
• Holistic hardware/software codesign: Batch normalization across reference temperatures, mapping optimization, and write-verify scheduling jointly deliver sub-1% accuracy drop across $25–100^\circ$C with $>100\times$ defect-tolerance boost. Layer-wise SNR allocation and noise-shaped activation further minimize energy while maintaining robustness (Fahimi et al., 2021).

6. Advanced Learning Rules, Temporal and Spiking Processing

Emerging analog ReRAM synaptic circuits extend beyond static MACs to implement online learning and temporal coding:

• Thermal eligibility trace encoding: 3D-integrated “neoHebbian” synapses combine a ReRAM cell for weight and a resistive heater for the eligibility trace, storing the latter as local temperature rise. This supports three-factor learning rules (e.g., e-prop RL) in analog hardware, with energy per update ~$5$ pJ, sub-10 ns writes, and compact $1.9~\mu\text{m}^2$ area, outperforming PCM and CMOS eligibility-trace designs (Pande et al., 2024).
• Dendritic temporal processing: DenRAM integrates programmable delay elements (via RRAM $RC$ circuits) and analog weight storage in dendritic branches, enabling temporal coincidence detection and efficient spatio-temporal pattern recognition. Experimental implementations achieve $>95\%$ benchmark accuracy with $5\times$ lower power and $10–100\times$ smaller memory than iso-accuracy SNNs with recurrence (DAgostino et al., 2023).
• Multi-level/compound bisable synapses: Compound bistable RRAM arrays in parallel (“dendritic learning”) yield bio-plausible multi-level STDP by mapping attenuation across branches to the stochastic device switching probability, thus achieving analog-like weight updates and double-exponential timing windows, even with strictly binary RRAM physics (Wu et al., 2016).

7. Performance Metrics, Limitations, and Commercialization Outlook

Experimental realizations demonstrate worst-case per-MAC power as low as 1.1 mW for 8-bit analog crossbar convolutions, with area per MAC reduced up to $8\times$ and classification accuracy loss $<0.5\%$ compared to full-precision baselines (Eshraghian et al., 2019). Bulk tri-layer RRAMs enable per-MVM energies of $\sim$1 pJ/MAC, an order of magnitude below SRAM baselines, with compact BEOL integration and high retention/endurance (Park et al., 2023). RACA-style architectures eliminate intermediate ADC/DAC overhead, dropping inference energy and area by up to 58% and 38%, respectively (Dang et al., 2024).

Critical limitations remain. Frequency-multiplexed analog crossbars face crosstalk, scaling, and phase-alignment constraints; bulk RRAMs require double device area for differential encoding but offer superior linearity and yield. Defect handling at array scale, especially for large crossbars, demands continual innovation in mapping, calibration, and compensation. Relaxation-aware multi-level programming currently achieves 2 bits/cell at scale; further improvements will rely on stochastic noise modeling and in-depth error characterization (Erfanijazi et al., 2023).

A plausible implication is that the progress in analog ReRAM neuromorphic circuits is enabling scalable, energy-efficient, and robust in-memory neural computation across modalities—from convolutional and fully-connected nets to temporal, spiking, and online-learning architectures—providing a hardware substrate for truly brain-inspired and low-power edge AI (Eshraghian et al., 2019, Park et al., 2023, Pande et al., 2024, DAgostino et al., 2023, Dang et al., 2024).