VerilogCL: Contrastive Learning for Verilog Generation

• VerilogCL is a contrastive-learning framework that enhances LLM-based Verilog generation by distinguishing valid RTL from minimally perturbed erroneous variants.
• It employs minimal-error data augmentation, generating anchor, positive, and negative samples to train robust representations using triplet margin loss.
• A proactive screening module leveraging semantic embeddings and token-level uncertainty features filters low-confidence outputs, significantly improving compilation and functional success rates.

VerilogCL denotes, in its named form, a contrastive-learning framework for robust LLM-based Verilog generation. It augments a 7B code model with minimal-error data augmentation, triplet-margin contrastive learning, and a proactive screening module that combines semantic embeddings with token-level uncertainty features to filter low-confidence candidates during generation (Tan et al., 20 Apr 2026). In a broader interpretive sense, adjacent HDL-generation literature has also used “VerilogCL-like” to describe classification-centric or closed-loop Verilog generators, but the term most precisely refers to the validity-aware contrastive framework introduced in 2026 (Sun et al., 2024, Sun et al., 22 Jan 2025, Tan et al., 20 Apr 2026).

1. Problem domain and conceptual scope

VerilogCL addresses a recurrent failure mode in LLM-based RTL synthesis: generated Verilog may be syntactically plausible yet structurally invalid, or it may compile successfully while remaining functionally incorrect under testbench evaluation (Tan et al., 20 Apr 2026). The framework is motivated by two properties of HDL generation that the underlying paper treats as central: first, high-quality Verilog corpora are relatively scarce compared with software-code corpora; second, Verilog imposes unusually sharp local correctness constraints, so small perturbations can produce catastrophic failures.

The error taxonomy emphasized by VerilogCL includes punctuation errors such as missing semicolons, commas, and colons; keyword errors such as typos and mismatched begin/end; operator errors such as confusing = and <=, or logical and bitwise operators; declaration errors such as missing signal declarations, incorrect wire/reg typing, and incorrect port directions; and structural errors such as assign statements outside module scope and multiple drivers for the same signal (Tan et al., 20 Apr 2026). This framing is narrower than generic code generation: the target is not stylistic fluency, but a boundary between valid and erroneous RTL.

A common misconception is that VerilogCL is merely a post-hoc rejection filter. In fact, its central claim is representational: the model is trained to separate correct RTL from minimally perturbed erroneous RTL in latent space, and the decoding-time screening stage is built on top of that learned separation rather than replacing it (Tan et al., 20 Apr 2026).

2. Minimal-error augmentation and contrastive representation learning

The framework begins with minimal-error data augmentation. For each verified RTL module, VerilogCL constructs an anchor that is correct RTL, a positive sample obtained through semantics-preserving transformations such as variable renaming and equivalent logic restructuring, and a negative sample derived by injecting a single controlled error that makes the code syntactically invalid or functionally incorrect (Tan et al., 20 Apr 2026). Positives are checked with Yosys equivalence checking; negatives are retained only if they consistently produce compilation failures or functional mismatches.

The curated augmentation covers both combinational and sequential logic. The module categories explicitly listed are Boolean functions (and_gate, or_gate, not_gate, xor_gate), arithmetic (half_adder, full_adder, comparator), datapath (mux), codecs (decoder, encoder), storage (d_flip_flop), counters (counter), memory (ram, rom), and FSM (traffic_light_controller) (Tan et al., 20 Apr 2026). The final training set contains approximately 3,000 triplets.

Sequence representations are extracted from final-layer hidden states. If the adapted model produces

$H_x \in \mathbb{R}^{L \times D},$

VerilogCL defines a sequence-level embedding through max pooling: $f(x) = \mathrm{MaxPool}(H_x) \in \mathbb{R}^{D}.$ Training then uses a triplet margin loss

$$L_{CL} = \max\!\bigl(0,\; \|f(a) - f(p)\|_2 - \|f(a) - f(n)\|_2 + m \bigr),$$

where $a$ is the anchor, $p$ the positive, $n$ the negative, and $m$ the margin (Tan et al., 20 Apr 2026). The intended effect is to pull together embeddings of correct, semantically equivalent RTL while pushing away embeddings of minimally different erroneous variants.

The backbone is DeepSeek-Coder-7B-Instruct-v1.5, adapted with LoRA on attention projection layers only, with rank 32 and dropout 0.05. The reported training configuration uses bfloat16 precision, AdamW, learning rate $3 \times 10^{-5}$, batch size 8, and 10 epochs (Tan et al., 20 Apr 2026). This design choice is important because VerilogCL does not alter the transformer architecture; it alters the geometry of the representation space.

3. Proactive screening and decoding-time control

The second pillar of VerilogCL is a proactive screening module that operates during generation rather than only after a complete module has been emitted (Tan et al., 20 Apr 2026). The screening classifier uses a hybrid feature vector built from semantic and uncertainty signals.

The semantic component is the same max-pooled sequence embedding used in contrastive learning. The statistical component is extracted from token-level output scores and includes three groups of features. Aggregate uncertainty features include avg_nll, avg_entropy, max_nll, max_entropy, std_nll, and low_confidence_token_count. Spike-detection features include spike_num, mean_spike_value, std_spike_value, max_spike_value, and max_spike_token_uncertainty. Token-specific features include punct_mean_nll, keyword_mean_nll, and last_k_mean_nll (Tan et al., 20 Apr 2026). These are concatenated as

$$v_{\text{hybrid}} = [v_{\text{sem}};\; v_{\text{stat}}].$$

A lightweight binary classifier is then trained on these hybrid features. Its objective is binary cross-entropy: $$L_{Cls} = -\frac{1}{N} \sum_{i=1}^N \left[y_i \log(\hat{y}_i) + (1-y_i) \log(1-\hat{y}_i)\right],$$ with $f(x) = \mathrm{MaxPool}(H_x) \in \mathbb{R}^{D}.$0 for valid RTL and $f(x) = \mathrm{MaxPool}(H_x) \in \mathbb{R}^{D}.$1 for erroneous RTL (Tan et al., 20 Apr 2026). The classifier is trained after freezing the contrastively tuned LLM, with learning rate $f(x) = \mathrm{MaxPool}(H_x) \in \mathbb{R}^{D}.$2, batch size 8, dropout 0.1, 80/20 train-validation split, and 100 epochs.

At inference time, generation proceeds autoregressively with temperature 0.7 and top-p 0.95. Whenever the partial output reaches a statement boundary such as ;, end, endcase, or endmodule, the model computes $f(x) = \mathrm{MaxPool}(H_x) \in \mathbb{R}^{D}.$3, scores the partial continuation with the classifier, and rejects the continuation if the score falls below threshold $f(x) = \mathrm{MaxPool}(H_x) \in \mathbb{R}^{D}.$4, resampling once from that boundary (Tan et al., 20 Apr 2026). The paper reports that F1 peaks at threshold $f(x) = \mathrm{MaxPool}(H_x) \in \mathbb{R}^{D}.$5, but fixes $f(x) = \mathrm{MaxPool}(H_x) \in \mathbb{R}^{D}.$6 for subsequent experiments.

This architecture positions screening as a local, decoding-time validity controller. It neither enforces a formal grammar nor performs a full repair loop; instead, it acts as a learned soft constraint at statement boundaries.

4. Datasets, benchmarks, and evaluation protocol

VerilogCL’s training signal comes from the curated triplet corpus described above, but its evaluation is performed on public RTL-generation benchmarks: VerilogEval and RTLLM (Tan et al., 20 Apr 2026). VerilogEval is split into VerilogEval-human and VerilogEval-machine. RTLLM is evaluated in versions 1.1 and 2.0.

For VerilogEval, the reported metric is pass@k with $f(x) = \mathrm{MaxPool}(H_x) \in \mathbb{R}^{D}.$7 generated samples per problem and $f(x) = \mathrm{MaxPool}(H_x) \in \mathbb{R}^{D}.$8. For RTLLM, the paper reports pass@5 together with two “success rate” variants defined over $f(x) = \mathrm{MaxPool}(H_x) \in \mathbb{R}^{D}.$9 samples per problem: compilation success rate, meaning the fraction of generated candidates that compile successfully, and functional success rate, meaning the fraction that pass the testbench (Tan et al., 20 Apr 2026). All benchmark evaluation uses official testbenches and Synopsys VCS.

The framework is compared against Verilog-specific LLMs such as VerilogEval, MEV-LLM, BetterV-CodeQwen, RTLCoder, and OriGen; commercial models such as GPT-3.5, GPT-4, and Claude3-Sonnet; and open-source code models such as CodeLlama-7B-Instruct, CodeQwen1.5-7B-Chat, and the untuned DeepSeek-Coder-7B-Instruct-v1.5 backbone (Tan et al., 20 Apr 2026). The article’s central comparison, however, is against its own base model and its internal ablations: contrastive only, classifier only, and the full combined system.

5. Empirical performance and ablation structure

The reported gains are substantial on both VerilogEval and RTLLM. The clearest summary is the comparison between the base DeepSeek-7B model and the full VerilogCL system (Tan et al., 20 Apr 2026).

Benchmark	Base DeepSeek-7B	Full VerilogCL
VerilogEval-human pass@1 / pass@5 / pass@10	31.7 / 42.8 / 46.8	55.3 / 60.3 / 65.2
VerilogEval-machine pass@1 / pass@5 / pass@10	55.7 / 73.9 / 77.6	74.5 / 85.4 / 87.4
RTLLM v1.1 pass@5	37.9	70.5
RTLLM v2.0 pass@5	45.0	61.9

On RTLLM v1.1, compilation success rate improves from 0.71 to 0.94, and functional success rate improves from 0.32 to 0.57 (Tan et al., 20 Apr 2026). The framework also reports strong internal synergy. On RTLLM v1.1, the base model achieves 70.7% compilation success and 32.1% functional success; adding contrastive learning alone yields 78.8% and 39.4%; adding the classifier alone yields 74.5% and 36.2%; and combining both yields 94.0% and 56.6% (Tan et al., 20 Apr 2026). The same pattern appears on RTLLM v2.0, where the combined model reaches 89.3% compilation success and 49.8% functional success.

The classifier itself benefits directly from contrastive adaptation. Before contrastive tuning, classifier accuracy is 79.5% and F1 is 79.96%; after contrastive tuning, accuracy rises to 92.5% and F1 to 92.58% (Tan et al., 20 Apr 2026). The paper further reports PCA visualizations in which correct and erroneous RTL embeddings show heavy overlap before contrastive learning and substantially clearer separation afterward. This is consistent with the framework’s core thesis that reliability depends on sharpening a validity boundary in representation space, not solely on adding a verifier after generation.

6. Position in the literature, limitations, and research trajectory

VerilogCL sits within a rapidly diversifying body of HDL-generation research. Some adjacent works are “VerilogCL-like” in the sense that they replace single-shot prompting with structured intermediate artifacts and verification signals. “Classification-Based Automatic HDL Code Generation Using LLMs” defines a classification-centric pipeline that routes tasks into COMB, SEQU, or BEHAV procedures, uses information lists and type-specific intermediate representations, and integrates PyEDA and testbench-guided search (Sun et al., 2024). “Paradigm-Based Automatic HDL Code Generation Using LLMs” refines the same design philosophy with specialized paradigm blocks, multi-round search, fail-safe and short-cut modes, and measurable gains on VerilogEval-human and VerilogEval-machine (Sun et al., 22 Jan 2025). “AutoChip” exemplifies a different tradition: a closed-loop system in which the LLM iteratively repairs HDL based on Icarus Verilog compilation output and HDLBits-derived simulation feedback (Thakur et al., 2023).

Other neighboring lines of work emphasize different supervisory signals. “LLM for Verilog Generation with Code-Structure-Guided Reinforcement Learning” uses AST-based rewards and PPO-style reinforcement learning to shape generation toward code-structure similarity rather than latent validity boundaries (Wang et al., 2024). “Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form” shifts the problem entirely by having the LLM emit PLF or CNF and then deterministically converting that representation into Verilog, treating correctness as a property of the formal intermediate rather than direct RTL generation (Roy et al., 7 May 2025). “QiMeng-CRUX” introduces CRUX as a structured intermediate representation between natural language and Verilog, and jointly optimizes that intermediate space with downstream code generation (Huang et al., 25 Nov 2025). “EvolVE” treats Verilog generation and optimization as evolutionary search, combining MCTS, Idea-Guided Refinement, and Structured Testbench Generation, and reports 98.1% on VerilogEval v2 and 92% on RTLLM v2 (Hsin et al., 26 Jan 2026).

Within that broader landscape, VerilogCL is distinctive for making the validity boundary itself the primary training object. Its main limitations are also explicit. The contrastive dataset is approximately 3,000 triplets over 15 module types; the negative samples are rule-based synthetic perturbations; the framework is tailored to Verilog rather than SystemVerilog or VHDL; the modules are relatively small and largely single-module; and the decoding-time classifier performs only a single local resampling when a continuation is rejected (Tan et al., 20 Apr 2026). These constraints do not negate the reported benchmark gains, but they delimit the scope of the claims.

A plausible implication is that VerilogCL’s main contribution is methodological rather than merely benchmark-driven: it proposes that robust HDL generation can be improved by teaching a model to discriminate near-miss RTL errors in representation space and by exposing that discrimination signal during decoding. The framework’s future directions, as stated, include more complex RTL generation, integration with formal verification and PPA, extension to other HDLs, multimodal specifications, and transfer to other high-validity domains (Tan et al., 20 Apr 2026).