Zero-Shot RTL Code Generation with Attention Sink Augmented Large Language Models (2401.08683v1)

Abstract: The design and optimization of hardware have traditionally been resource-intensive, demanding considerable expertise and dependence on established design automation tools. This paper discusses the possibility of exploiting LLMs to streamline the code generation process in hardware design. In contrast to earlier studies, this paper aims to use LLMs that accepts high-level design specifications through a single prompt to generate corresponding Register-Transfer Level (RTL) code. The ability to use LLMs on RTL code generation not only expedites design iteration cycles but also facilitates the exploration of design spaces that have computational challenges for conventional techniques. Through our evaluation, we demonstrate the shortcoming of existing attention mechanisms, and present the abilities of LLMs to produce functional, optimized, and industry-standard compliant RTL code when a novel attention mechanism is used. These findings underscore the expanding role of LLMs in shaping the future landscape of architectural exploration and automation in hardware design.