ROIRC: Region-of-Interest Readout Circuit

• Region-of-Interest Readout Circuit (ROIRC) is an electronic architecture that selectively targets sensor zones for high-resolution data acquisition with minimal overhead.
• It integrates sensor-specific front ends, FPGA control, and dynamic sequencer logic to optimize readout time and data bandwidth while maintaining signal quality.
• Applications span particle detection, quantum imaging, and astronomical systems, achieving significant data reduction and noise improvement in critical regions.

The Region-of-Interest Readout Circuit (ROIRC) is an electronic architecture designed to selectively acquire data from spatial and/or temporal regions of interest within large-scale image sensors, pixel arrays, and multi-channel detector systems. By limiting high-resolution or high-rate readout to user-defined critical regions and minimizing acquisition elsewhere, ROIRC implementations achieve massive reductions in readout time, data bandwidth, and power consumption while preserving essential signal fidelity in targeted zones. The concept spans nondestructive charge imagers (e.g., Skipper CCDs), waveform samplers (MCP-based detectors), large gas pixel arrays, and wire-based TPCs, with corresponding hardware and firmware optimizations.

1. Hardware Architecture and Front-End Design

ROIRC architectures are typified by their sensor-specific front ends, programmable sampling stages, and digital control/processing modules.

• In Skipper-CCD systems, the analog chain comprises a floating-gate output, correlated-double sampling (CDS) frontend, and high-bit SAR ADCs (18 bits @ 15 MS/s) (Chierchie et al., 2020). The key non-destructive feature allows repeated charge measurement per pixel, with a programmable per-pixel sample count.
• Gas Pixel Detectors and large pixel arrays embed scanning modules within the ASIC, accompanied by FPGA-based block addressing logic. Sentinel pixel strategies enable coarse event detection followed by fine block-wise acquisition, resulting in single-buffer, single-ADC topologies (Zhou et al., 19 Nov 2025).
• For time-of-propagation Cherenkov detectors (Belle II TOP), ROIRC is implemented via switched-capacitor array ASICs and comparator-triggered sampling, interfaced to FPGA SoCs that define ROI windows upon event triggers (Kotchetkov et al., 2018).
• In wire-based LAr-TPCs, ROI logic resides on dedicated FPGAs interfacing with fast ADCs (e.g., 10 bits @ 40 MHz), and region selection is enabled via onboard sliding-window hit-finding, majority logic, and compressed data buffers (Baibussinov et al., 2010).

Key architectural features are summarized below.

Detector Class	Sensing Front-End	ROI Engine Location	ADC Spec
Skipper CCD	Floating-gate + CDS	Artix-7 FPGA	18-bit, 15 MS/s
Gas Pixel (Topmetal-L)	CSA + source-follower	ASIC + FPGA	12-bit, 40 MSPS
MCP-PMT (Belle II)	SCA ASIC + comparator	FPGA SoC	Wilkinson, 12-bit
LAr-TPC	CSA + Shaper	FPGA (SuperDaedalus)	10-bit, 40 MHz

FPGA selection, buffer sizing, and clock domain management (e.g., multiple asynchronous environments (Arnold et al., 2017)) are critical for sustaining low-latency, high-throughput readout across diverse detector contexts.

2. ROI Definition and Sequencer Logic

The ROIRC's core function is dynamic allocation of readout resources. ROI definition is typically managed by digital sequencers or state machines that interpret user-uploaded recipes, static masks, or event-driven trigger patterns. Schemes include:

• Uploadable ROI "recipes" specifying rectangular, pixel-list, or parametrically defined zones, each paired with a desired integration count $N$ (Chierchie et al., 2020).
• Sentinel pixel detection: periodic sparse scanning identifies candidate signal events, which, upon threshold breach, spawn block-wise region definitions grouped and merged in real time on the FPGA (Zhou et al., 19 Nov 2025).
• In event-driven systems (Belle II TOP), global triggers synchronize per-channel comparators, with the firmware defining local memory windows around flagged hits (Kotchetkov et al., 2018).
• Dynamic ROI/EOI controllers adapt integration depth on-the-fly by evaluating charge or energy-of-interest criteria, switching between shallow and deep sampling on a per-pixel basis (Chierchie et al., 2021).

These methods enable direct mapping of physical event topology to digital sampling, and facilitate scaling to very large arrays via lookup tables, dynamic region maps, or temporally aligned buffer pointers. For TPC systems, majority logic coupled with PEAK stretching enables robust spatial segmentation (Baibussinov et al., 2010).

3. Signal Acquisition and Measurement Protocols

Measurement protocols within ROIRC frameworks are tailored to the underlying sensor technology:

• Skipper-CCD: For each pixel $i$, $N_i$ non-destructive samples are performed, each via dual-slope integration and baseline subtraction. The final value $P_{i,skp}$ is averaged, with the noise scaling as $\sigma(N)=\sigma_0/\sqrt{N}$ (Chierchie et al., 2020).
• Topmetal-L/GPD: Sentinel detection computes $\Delta V(i,j)$, triggering blockwise acquisition. Each block readout is optimized for latency ($T_{blk}\sim 36\,\mu$s), and merged blocks avoid redundancy (Zhou et al., 19 Nov 2025).
• SCA-based systems: When a trigger is received, a programmable window ($M$ samples, $W_{ROI}=M\cdot\Delta t$) is digitized using ADCs, and zero-suppression or feature extraction is performed downstream (Kotchetkov et al., 2018).
• TPC wire arrays: Continuous hit-finding via double-rebinning/sliding-window algorithm flags wires with signals $S(t)\geq Q_{thr}$, with majority logic and spatial stretching forming the final ROI trigger. Data compression via difference encoding or block packing is performed prior to DAQ (Baibussinov et al., 2010).

Across systems, baseline correction and noise reduction (e.g., median subtraction in Skipper-CCD (Chierchie et al., 2020)) are essential to preserve accuracy under variable clock patterns and environmental drift.

4. Data Reduction, Performance Metrics, and Trade-Offs

ROIRC circuits deliver large reductions in readout time and bandwidth by restricting intensive acquisition to ROIs. Key metrics include:

• Noise reduction follows $\sigma(N)=\sigma_0/\sqrt{N}$; high-$N$ regions reach deep sub-electron RMS at the cost of $100-1000\times$ increased dwell per pixel (Chierchie et al., 2020, Chierchie et al., 2021).
• Readout time per pixel is $T(N)=N t_{read}$; total frame time $T_{total}=\sum_i N_i t_{read}$ is minimized by assigning $N_i=1$ to noncritical regions (Chierchie et al., 2020).
• Data reduction in GPDs is $>500\times$ (361 px/event vs. 182272 px/event) for sentinel-triggered blocks (Zhou et al., 19 Nov 2025).
• For high-rate waveform detectors, ROI sample readout improves event throughput by a factor $G=N_{full}/N_{ROI}$, with dead-time dropping from full-buffer times ($\sim \mu$s) to $<$150 ns per event (Seljak et al., 16 Jun 2024).
• FPGA-based LAr-TPC systems compress raw data by $\sim4\times$ and can trigger on $\sim1$ MeV energy deposition, with board-level latency $\lesssim55\,\mu$s (Baibussinov et al., 2010). Data volume reductions reach $10^4-10^5$ for anti-neutrino detectors like SoLid (Arnold et al., 2017).

Trade-offs include more complex digital firmware, per-pixel or per-block lookup logic, and calibration requirements to correct for nonuniform baseline shifts or artifact introduction during sparse clocking.

5. Implementation Details and System Integration

Systems typically deploy ROIRC logic on commercial or custom FPGA platforms, often partitioned into dedicated soft-core processor blocks (e.g., μBlaze) and high-speed DMA engines:

• Per-channel lookup tables for $N_i$ assignment are typically sized to array dimensions, requiring efficient on-chip storage and mapping logic (Chierchie et al., 2020, Kotchetkov et al., 2018).
• Buffer sizing is governed by trigger latency and desired ROI window length: e.g., $N_{\text{buffer}}=f_s(\tau_{max}+W_{ROI})$ (Arnold et al., 2017).
• Block-wise ROI assembly, zero-suppression, and packetization leverage parallel-PHY links (e.g., 1–2.5 Gb/s optical, TCP/IP packets) with cyclic redundancy check and flow control (Kotchetkov et al., 2018).
• Power consumption drops sharply with single-buffer designs: e.g., $33\,$mW in Topmetal-L ROI scan vs. $528\,$mW in rolling shutter (Zhou et al., 19 Nov 2025).

System scalability is realized by modularizing per-channel ROI FSMs and read buses, synchronizing bank pointers via global counters, and aggregating data in downstream FPGAs or DAQ middleware (Seljak et al., 16 Jun 2024).

6. Applications, Limitations, and Future Directions

ROIRC is integral to next-generation particle detection, astronomical imaging, quantum metrology, and medical imaging. Applications include:

• Ultra-low-noise charge counting (Skipper-CCD) for quantum imaging, exoplanet spectrometry, and dark matter searches (Chierchie et al., 2020, Chierchie et al., 2021).
• Gas Pixel Detectors for X-ray polarimetry (e.g., POLAR-2/LPD) and large-area imagers (Zhou et al., 19 Nov 2025).
• High-throughput photon timing (Belle II TOP) for particle identification (Kotchetkov et al., 2018).
• Wire-based readout for neutrino observatories (ICARUS, SoLid) (Baibussinov et al., 2010, Arnold et al., 2017).

Limitations derive from sensor physics (nondestructive readout is required for repeated sampling), calibration complexity (especially with per-pixel clock pattern variation), and the overhead inherent in highly fragmented ROI maps. For destructive sensors (EMCCD, SiPM, SPAD), ROIRC principles may be adapted by introducing analog memory or charge caching, but direct repeat-and-average is not possible (Chierchie et al., 2021).

Ongoing research directions involve:

• Dynamic, adaptive ROI sequencing based on real-time event morphology,
• Deep integration of ROI buffer logic within ASICs to enable sub-μs latencies,
• Advanced lossless or near-lossless compression strategies for sparse events,
• Extension to multi-parameter ROI (e.g., time, energy, topology), facilitating multimodal event characterization.

ROIRC has become indispensable in maximizing the efficiency and sensitivity of modern detector systems across scientific domains.