HGCROC: High Granularity Calorimeter Readout Chip

Updated 11 August 2025

HGCROC is a custom ASIC developed for the CMS HGCAL upgrade, offering high precision digitization with dual gain paths and a 15-bit dynamic range.
It employs a sophisticated signal processing chain with ADC and ToT channels to achieve sub-50 ps timing resolution and energy measurements with nonlinearity below 5%.
Its scalable architecture enables seamless integration with silicon and scintillator sensors, robust buffering, and advanced trigger primitive generation for HL-LHC challenges.

The High Granularity Calorimeter Readout Chip (HGCROC) is a custom front-end application-specific integrated circuit (ASIC) designed for the CMS High Granularity Calorimeter (HGCAL) upgrade at the High-Luminosity Large Hadron Collider (HL-LHC). Engineered to digitize the signals from millions of highly granular silicon and scintillator sensors in radiation-intense, high-rate environments, the HGCROC embodies advanced analog and digital processing, robust radiation hardness, and precise time and amplitude resolution. The integration of the HGCROC within the calorimeter modules is central to the overall energy, position, and time measurement strategy used by CMS for precision calorimetry and trigger primitives in complex event topologies.

1. Architecture and Signal Processing

The HGCROC is architected to manage the simultaneous demands of extreme channel density, wide dynamic range, and low power operation under harsh radiation exposure (Pitters, 2018, Quast, 2021). Key features include:

Dynamic Range: Capable of resolving input charge from 0.4 fC up to 10 pC (15-bit resolution) (Pitters, 2018), allowing accurate measurement of both minimum ionizing particles and the largest electromagnetic shower signals.
Dual Gain and Time Processing: Incorporates at least two gain paths for amplitude digitization with a 10-bit ADC (for small signals) and a time-over-threshold (ToT) stage for large signals, ensuring linearity over the full range (Quast, 2021).
Timing: Provides a dedicated time-of-arrival (TOA) channel with temporal binning at the level of 50 ps, supported by an internal 10-bit TDC (Pitters, 2018, Quast, 2021), crucial for pileup suppression and event vertex association.
Low Power and Radiation Hardness: Each channel operates with a strict analog front-end power budget below 10–20 mW and is implemented in TSMC’s 130 nm CMOS for radiation tolerance up to 150 MRad (qualified up to 400 MRad) (Pitters, 2018, Quast, 2021).
On-chip Buffering and Auto-trigger: Large local buffers support the trigger latency constraints of HL-LHC (up to 12.5 μs) and facilitate self-triggered readout architectures (Acar et al., 2020).

The signal processing chain encompasses preamplification, gain staging, amplitude and timing digitization, and multi-path outputs, enabling both full readout and trigger-specific fast path delivery.

2. Integration with Calorimeter Sensors and Module Electronics

The HGCROC is designed to interface directly with hexagonal, n-in-p silicon diodes (~0.5–1.1 cm² pad size) and tile-scintillator/SiPM assemblies (Paulitsch, 2020, Quast, 2021). Sensor and module integration features:

Sensor Interface: Robust wirebonding to dedicated PCBs (Hexaboards) with inward extensions of guard and edge rings for reliable electrical and mechanical coupling; the frontside biasing method eliminates fragility due to thin backside metalization, enhancing production yield and reliability (Paulitsch, 2020).
Module Stacking: ASICs are mounted on readout PCBs with direct wire connections to sensors, integrated cooling infrastructure, and power distribution systems. The CO₂ cooling scheme maintains sensor temperatures below –30°C, mitigating leakage and radiation damage (Quast, 2021).
Data and Trigger Paths: The chip outputs are split into data (for ECON-D zero-suppression and backend readout) and trigger (for ECON-T formation of primitives), achieving substantial data rate reduction by hierarchical compression (Quast, 2021, Lupi et al., 5 Nov 2024).

In total, HGCROC chips will be produced and deployed in quantities exceeding 27,000, collectively serving more than six million sensor channels in CMS HGCAL (Quast, 2021).

3. Performance: Energy, Position, and Time Resolution

Comprehensive module and beam test campaigns have demonstrated the performance of HGCROC-based calorimeter systems (Acar et al., 2022, Awes et al., 2019):

Energy Measurement:
- Dual-path amplitude processing (ADC for low signals, ToT for high signals) achieves a linear response from MIPs to TeV-scale deposits (Quast, 2021).
- Calorimeter energy reconstruction via weighted sums,
$E_\text{rec} = \sum_i w_i E_i,$

with channel-specific calibration factors $w_i$ ensures nonlinearity below 5% over the relevant energy range (Acar et al., 2022).
Resolution:
- Stochastic terms as low as 25%/ $\sqrt{E}$ and constant terms below 1% observed in prototype calorimeters (Pitters, 2018, Awes et al., 2019, Acar et al., 2022).
- Sub-mm spatial resolution is achievable for electromagnetic showers using pixelated silicon sensors and advanced centroid techniques (Awes et al., 2019, Peitzmann et al., 2022).
Timing:
- Achieves per-channel time resolution of $\sim$ 50 ps, with potential for sub-15 ps at high signal amplitudes (Pitters, 2018, Quast, 2021).
- Timing information critical for pileup rejection, with detailed synchronization and timestamping throughout the DAQ chain (Acar et al., 2020).

These capabilities enable robust identification of shower constituents, precision particle flow reconstruction, and efficient trigger primitive formation.

4. System-Level Readout and Data Concentration

Beyond the primary front-end digitization, HGCROC outputs are managed by the Endcap Concentrator (ECON) ASICs (both ECON-T for trigger and ECON-D for data) (Lupi et al., 5 Nov 2024). The readout chain operates as follows:

Data Processing Pipeline:

| Stage | ASIC/Module | Function | |-------------|------------------|------------------------------------------| | Front-end | HGCROC | Charge & timing digitization, buffering | | Concentrator| ECON-D, ECON-T | Zero-suppression, trigger primitive gen. | | Back-end | lpGBT | Optical data transmission |

Trigger/Timing Alignment: Shared clock and control infrastructure ensure precise temporal alignment across up to six HGCROC chips per ECON.
Error Mitigation: Triple Modular Redundancy and Error Correction Coding guarantee reliable operation in the presence of single-event effects and high-energy hadron flux ( $\Phi_{HEH} \approx 3 \cdot 10^6$ cm⁻² s⁻¹) (Lupi et al., 5 Nov 2024).
DAQ System: FPGA-based DAQ boards and modular firmware aggregate channel data at readout rates up to 40 Hz for test beams, targeting $O$ (750 kHz) L1 rates in final deployment (Acar et al., 2020).

Rigorous Universal Verification Methodology (UVM)-based simulation campaigns certify the functional integrity, error resilience, and timing precision of the complete ASIC chain (Lupi et al., 5 Nov 2024).

5. Calorimeter Design Optimization and Impact on HGCROC Performance

Recent studies have explored the influence of longitudinal calorimeter structure on HGCROC performance (Borysov et al., 29 Sep 2024). Key insights include:

Longitudinal Segmentation: Non-uniform sampling layouts, optimized via genetic algorithms and Pareto front multi-objective sorting, directly enhance energy resolution and directional measurement precision by concentrating sensor density at the shower maxima.
Calibration Strategies: Semi-analytical approaches using detailed GEANT4-based simulations generate layer-wise calibration constants ( $w_i$ ) suitable for direct algorithmic incorporation into HGCROC signal weighting and dynamic range settings.
Implications: Optimized structure improves signal-to-noise ratios, minimizes calibration uncertainty, and ensures HGCROC digitizes data with maximal informational content—crucially benefiting both offline analysis and real-time trigger processing.

The HGCROC concept generalizes to other high rate, high granularity calorimeter systems (Fouz, 2012, Grenier, 2016, Pinto, 2020, Peitzmann et al., 2022):

Comparison to HARDROC, SPIROC2E, and SKIROC: While HARDROC (SDHCAL) and SPIROC2E (AHCAL) employ similar semi-digital or analog-digital architecture for lower rate environments, HGCROC expands channel density, radiation tolerance, and time precision appropriate for HL-LHC (Fouz, 2012, Pinto, 2020).
Digital Pixel Readout: ALPIDE-based digital pixel calorimetry (EPICAL-2) demonstrates alternative approaches for extreme granularity and two-shower separation capability, informing future HGCROC architectural extensions (Peitzmann et al., 2022).
Trigger Algorithms: HGCROC delivers structured enough outputs for fast convolutional neural network (CNN) algorithms deployed on FPGAs for real-time long-lived particle identification in HL-LHC contexts (Alimena et al., 2020).

7. Future Directions and Qualification

Ongoing developments focus on:

Mass Production and Qualification: Pre-series production and extensive irradiation campaigns validate large-scale HGCROC deployment and sensor-ASIC interfacing (Paulitsch, 2020, Quast, 2021).
Firmware and System Integration: Continuous integration, UVM-based regression testing, and tight clock control in multi-ASIC environments support long-term reliability (Lupi et al., 5 Nov 2024).
Algorithmic Upgrades: Enhanced calibration, timing extraction, and pattern recognition at both ASIC and system levels advance CMS calorimetry capabilities for future challenge scenarios (Borysov et al., 29 Sep 2024, Alimena et al., 2020).

In summary, the HGCROC stands as a pivotal readout platform for highly granular, precision calorimetry in next-generation collider experiments, integrating advanced signal processing, robust engineering for hostile operational environments, and a scalable architecture for the physics goals of CMS at the HL-LHC and beyond.